1 /* 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)zsvar.h 7.1 (Berkeley) 07/13/92 12 * 13 * from: $Header: zsvar.h,v 1.4 92/06/17 05:35:54 torek Exp $ (LBL) 14 */ 15 16 /* 17 * Software state, per zs channel. 18 * 19 * The receive ring size and type are carefully chosen to make the 20 * zs hardware interrupt handler go fast. We need 8 bits for the 21 * received character and 8 bits for the corresponding RR1 status. 22 * The character is known to be in the upper byte of the pair. 23 */ 24 #define ZLRB_RING_SIZE 256 25 #define ZLRB_RING_MASK 255 26 27 struct zs_chanstate { 28 struct zs_chanstate *cs_next; /* linked list for zshard() */ 29 volatile struct zschan *cs_zc; /* points to hardware regs */ 30 int cs_unit; /* unit number */ 31 struct tty *cs_ttyp; /* ### */ 32 33 /* 34 * We must keep a copy of the write registers as they are 35 * mostly write-only and we sometimes need to set and clear 36 * individual bits (e.g., in WR3). Not all of these are 37 * needed but 16 bytes is cheap and this makes the addressing 38 * simpler. Unfortunately, we can only write to some registers 39 * when the chip is not actually transmitting, so whenever 40 * we are expecting a `transmit done' interrupt the wreg array 41 * is allowed to `get ahead' of the current values. In a 42 * few places we must change the current value of a register, 43 * rather than (or in addition to) the pending value; for these 44 * cs_creg[] contains the current value. 45 */ 46 u_char cs_creg[16]; /* current values */ 47 u_char cs_preg[16]; /* pending values */ 48 u_char cs_heldchange; /* change pending (creg != preg) */ 49 50 /* 51 * The transmit byte count and address are used for pseudo-DMA 52 * output in the hardware interrupt code. PDMA can be suspended 53 * to get pending changes done; heldtbc is used for this. It can 54 * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state. 55 */ 56 int cs_tbc; /* transmit byte count */ 57 caddr_t cs_tba; /* transmit buffer address */ 58 int cs_heldtbc; /* held tbc while xmission stopped */ 59 60 /* 61 * Printing an overrun error message often takes long enough to 62 * cause another overrun, so we only print one per second. 63 */ 64 long cs_rotime; /* time of last ring overrun */ 65 long cs_fotime; /* time of last fifo overrun */ 66 67 /* pure software data, per channel */ 68 int cs_speed; /* default baud rate (from ROM) */ 69 char cs_softcar; /* software carrier */ 70 char cs_conk; /* is console keyboard, decode L1-A */ 71 char cs_brkabort; /* abort (as if via L1-A) on BREAK */ 72 char cs_kgdb; /* enter debugger on frame char */ 73 char cs_consio; /* port does /dev/console I/O */ 74 75 /* 76 * Status change interrupts merely copy the new status and 77 * schedule a software interrupt to deal with it. To make 78 * checking easier, cs_rr0 is guaranteed nonzero on status 79 * changes. cs_txint indicates a software transmit interrupt 80 * (a txint where cs_tbc was 0). A software receive interrupt 81 * is implicit in cs_rbget != cs_rbput. 82 */ 83 u_char cs_txint; /* software tx interrupt */ 84 u_short cs_rr0; /* rr0 | 0x100, after change */ 85 u_int cs_rbget; /* receive ring buffer `get' index */ 86 volatile u_int cs_rbput; /* receive ring buffer `put' index */ 87 u_short cs_rbuf[ZLRB_RING_SIZE];/* packed data: (char << 8) + rr1 */ 88 }; 89 90 /* 91 * Macros to read and write individual registers (except 0) in a channel. 92 * 93 * On the SparcStation the 1.6 microsecond recovery time is 94 * handled in hardware. 95 */ 96 #define ZS_READ(c, r) ((c)->zc_csr = (r), (c)->zc_csr) 97 #define ZS_WRITE(c, r, v) ((c)->zc_csr = (r), (c)->zc_csr = (v)) 98