xref: /csrg-svn/sys/pmax/include/dc7085cons.h (revision 63217)
152131Smckusick /*
2*63217Sbostic  * Copyright (c) 1992, 1993
3*63217Sbostic  *	The Regents of the University of California.  All rights reserved.
452131Smckusick  *
552131Smckusick  * This code is derived from software contributed to Berkeley by
656821Sralph  * Ralph Campbell and Rick Macklem.
752131Smckusick  *
852131Smckusick  * %sccs.include.redist.c%
952131Smckusick  *
10*63217Sbostic  *	@(#)dc7085cons.h	8.1 (Berkeley) 06/10/93
1152131Smckusick  *
1252131Smckusick  * dc7085.h --
1352131Smckusick  *
1452131Smckusick  *     	Definitions for the dc7085 chip.
1552131Smckusick  *
1652131Smckusick  *	Copyright (C) 1989 Digital Equipment Corporation.
1752131Smckusick  *	Permission to use, copy, modify, and distribute this software and
1852131Smckusick  *	its documentation for any purpose and without fee is hereby granted,
1952131Smckusick  *	provided that the above copyright notice appears in all copies.
2052131Smckusick  *	Digital Equipment Corporation makes no representations about the
2152131Smckusick  *	suitability of this software for any purpose.  It is provided "as is"
2252131Smckusick  *	without express or implied warranty.
2352131Smckusick  *
2452131Smckusick  * from: $Header: /sprite/src/kernel/dev/ds3100.md/RCS/dc7085.h,
2552131Smckusick  *	v 1.4 89/08/15 19:52:46 rab Exp $ SPRITE (DECWRL)
2652131Smckusick  */
2752131Smckusick 
2852131Smckusick #ifndef _DC7085
2952131Smckusick #define _DC7085
3052131Smckusick 
3152131Smckusick typedef volatile struct dc7085regs {
3252131Smckusick 	u_short	dc_csr;		/* control and status (R/W) */
3352131Smckusick 	u_short	pad0[3];
3452131Smckusick 	short	dc_rbuf_lpr;	/* receiver data (R), line params (W) */
3552131Smckusick 	u_short	pad1[3];
3652131Smckusick 	u_short	dc_tcr;		/* transmitter control (R/W) */
3752131Smckusick 	u_short	pad2[3];
3852131Smckusick 	u_short	dc_msr_tdr;	/* modem status (R), transmit data (W) */
3952131Smckusick } dcregs;
4052131Smckusick #define dc_rbuf	dc_rbuf_lpr
4152131Smckusick #define dc_lpr	dc_rbuf_lpr
4252131Smckusick #define dc_msr	dc_msr_tdr
4352131Smckusick #define dc_tdr	dc_msr_tdr
4452131Smckusick 
4552131Smckusick /*
4652131Smckusick  * Control status register bits.
4752131Smckusick  */
4852131Smckusick #define	CSR_TRDY	0x8000
4952131Smckusick #define CSR_TIE		0x4000
5052131Smckusick #define	CSR_TX_LINE_NUM	0x0300
5152131Smckusick #define	CSR_RDONE	0x0080
5252131Smckusick #define	CSR_RIE		0x0040
5352131Smckusick #define CSR_MSE		0x0020
5452131Smckusick #define CSR_CLR		0x0010
5552131Smckusick #define CSR_MAINT	0x0008
5652131Smckusick 
5752131Smckusick /*
5852131Smckusick  * Receiver buffer register bits.
5952131Smckusick  */
6052131Smckusick #define	RBUF_DVAL		0x8000
6152131Smckusick #define RBUF_OERR		0x4000
6252131Smckusick #define RBUF_FERR		0x2000
6352131Smckusick #define RBUF_PERR		0x1000
6452131Smckusick #define RBUF_LINE_NUM		0x0300
6552131Smckusick #define RBUF_LINE_NUM_SHIFT	8
6652131Smckusick #define RBUF_CHAR		0x00FF
6752131Smckusick 
6852131Smckusick /*
6952131Smckusick  * Transmit control register values.
7052131Smckusick  */
7152131Smckusick #define TCR_DTR2		0x400
7252131Smckusick #define TCR_EN3			0x008
7352131Smckusick #define TCR_EN2			0x004
7452131Smckusick #define TCR_EN1			0x002
7552131Smckusick #define TCR_EN0			0x001
7652131Smckusick 
7752745Sralph #define TCR_RTS2		0x800
7852745Sralph #define TCR_RTS3		0x200
7952745Sralph #define TCR_DTR3		0x100
8052745Sralph 
8152131Smckusick /*
8252131Smckusick  * Line parameter register bits.
8352131Smckusick  */
8452131Smckusick #define	LPR_RXENAB	0x1000
8552131Smckusick #define LPR_B50		0x0000
8652131Smckusick #define LPR_B75		0x0100
8752131Smckusick #define LPR_B110	0x0200
8852131Smckusick #define LPR_B134	0x0300
8952131Smckusick #define LPR_B150	0x0400
9052131Smckusick #define LPR_B300	0x0500
9152131Smckusick #define LPR_B600	0x0600
9252131Smckusick #define LPR_B1200	0x0700
9352131Smckusick #define LPR_B1800	0x0800
9452131Smckusick #define LPR_B2000	0x0900
9552131Smckusick #define LPR_B2400	0x0A00
9652131Smckusick #define LPR_B3600	0x0B00
9752131Smckusick #define	LPR_B4800	0x0C00
9852131Smckusick #define LPR_B7200	0x0D00
9952131Smckusick #define LPR_B9600	0x0E00
10052745Sralph #define LPR_B19200	0x0F00
10152745Sralph #define LPR_B38400	0x0F00
10252131Smckusick #define LPR_OPAR	0x0080
10352131Smckusick #define LPR_PARENB	0x0040
10452131Smckusick #define LPR_2_STOP	0x0020
10552131Smckusick #define LPR_8_BIT_CHAR	0x0018
10652131Smckusick #define LPR_7_BIT_CHAR	0x0010
10752131Smckusick #define LPR_6_BIT_CHAR	0x0008
10852131Smckusick #define LPR_5_BIT_CHAR	0x0000
10952131Smckusick 
11052131Smckusick /*
11152131Smckusick  * Modem status register bits.
11252131Smckusick  */
11352131Smckusick #define	MSR_DSR2	0x0200
11452131Smckusick 
11552745Sralph #define	MSR_RI2		0x0800
11652745Sralph #define	MSR_CD2		0x0400
11752745Sralph #define	MSR_CTS2	0x0100
11852745Sralph #define	MSR_RI3		0x0008
11952745Sralph #define	MSR_CD3		0x0004
12052745Sralph #define	MSR_DSR3	0x0002
12152745Sralph #define	MSR_CTS3	0x0001
12252745Sralph 
12352131Smckusick /*
12452131Smckusick  * The four serial ports.
12552131Smckusick  */
12656821Sralph #define DCKBD_PORT	0
12756821Sralph #define DCMOUSE_PORT	1
12856821Sralph #define DCCOMM_PORT	2
12956821Sralph #define DCPRINTER_PORT	3
13052131Smckusick 
13152131Smckusick /* bits in dm lsr, copied from dmreg.h */
13252131Smckusick #define	DML_DSR		0000400		/* data set ready, not a real DM bit */
13352131Smckusick #define	DML_RNG		0000200		/* ring */
13452131Smckusick #define	DML_CAR		0000100		/* carrier detect */
13552131Smckusick #define	DML_CTS		0000040		/* clear to send */
13652131Smckusick #define	DML_SR		0000020		/* secondary receive */
13752131Smckusick #define	DML_ST		0000010		/* secondary transmit */
13852131Smckusick #define	DML_RTS		0000004		/* request to send */
13952131Smckusick #define	DML_DTR		0000002		/* data terminal ready */
14052131Smckusick #define	DML_LE		0000001		/* line enable */
14152131Smckusick 
14252131Smckusick #endif /* _DC7085 */
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