1*56818Sralph /*- 2*56818Sralph * Copyright (c) 1992 The Regents of the University of California. 3*56818Sralph * All rights reserved. 4*56818Sralph * 5*56818Sralph * This code is derived from software contributed to Berkeley by 6*56818Sralph * Ralph Campbell and Rick Macklem. 7*56818Sralph * 8*56818Sralph * %sccs.include.redist.c% 9*56818Sralph * 10*56818Sralph * @(#)xcfbreg.h 7.1 (Berkeley) 11/15/92 11*56818Sralph */ 12*56818Sralph 13*56818Sralph /* 14*56818Sralph * Mach Operating System 15*56818Sralph * Copyright (c) 1991,1990,1989 Carnegie Mellon University 16*56818Sralph * All Rights Reserved. 17*56818Sralph * 18*56818Sralph * Permission to use, copy, modify and distribute this software and its 19*56818Sralph * documentation is hereby granted, provided that both the copyright 20*56818Sralph * notice and this permission notice appear in all copies of the 21*56818Sralph * software, derivative works or modified versions, and any portions 22*56818Sralph * thereof, and that both notices appear in supporting documentation. 23*56818Sralph * 24*56818Sralph * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 25*56818Sralph * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 26*56818Sralph * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 27*56818Sralph * 28*56818Sralph * Carnegie Mellon requests users of this software to return to 29*56818Sralph * 30*56818Sralph * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 31*56818Sralph * School of Computer Science 32*56818Sralph * Carnegie Mellon University 33*56818Sralph * Pittsburgh PA 15213-3890 34*56818Sralph * 35*56818Sralph * any improvements or extensions that they make and grant Carnegie Mellon 36*56818Sralph * the rights to redistribute these changes. 37*56818Sralph */ 38*56818Sralph /* 39*56818Sralph * Defines for the Inmos IMS-G332 Colour video controller 40*56818Sralph * Author: Alessandro Forin, Carnegie Mellon University 41*56818Sralph * See: IMS G332 Colour Video Controller, 1990 Databook, pg 139-163, 42*56818Sralph * Inmos, Ltd. 43*56818Sralph */ 44*56818Sralph 45*56818Sralph #define IMS332_ADDRESS 0xbc140000 46*56818Sralph #define VRAM_OFFSET 0x2000000 47*56818Sralph #define IMS332_RESET_ADDRESS 0xbc040100 48*56818Sralph 49*56818Sralph /* 50*56818Sralph * Although the chip is built to be memory-mapped 51*56818Sralph * it can be programmed for 32 or 64 bit addressing. 52*56818Sralph * Moreover, the hardware bits have been twisted 53*56818Sralph * even more on the machine I am writing this for. 54*56818Sralph * So I'll just define the chip's offsets and leave 55*56818Sralph * it to the implementation to define the rest. 56*56818Sralph */ 57*56818Sralph #define IMS332_REG_BOOT 0x000 /* boot time config */ 58*56818Sralph 59*56818Sralph #define IMS332_REG_HALF_SYNCH 0x021 /* datapath registers */ 60*56818Sralph #define IMS332_REG_BACK_PORCH 0x022 61*56818Sralph #define IMS332_REG_DISPLAY 0x023 62*56818Sralph #define IMS332_REG_SHORT_DIS 0x024 63*56818Sralph #define IMS332_REG_BROAD_PULSE 0x025 64*56818Sralph #define IMS332_REG_V_SYNC 0x026 65*56818Sralph #define IMS332_REG_V_PRE_EQUALIZE 0x027 66*56818Sralph #define IMS332_REG_V_POST_EQUALIZE 0x028 67*56818Sralph #define IMS332_REG_V_BLANK 0x029 68*56818Sralph #define IMS332_REG_V_DISPLAY 0x02a 69*56818Sralph #define IMS332_REG_LINE_TIME 0x02b 70*56818Sralph #define IMS332_REG_LINE_START 0x02c 71*56818Sralph #define IMS332_REG_MEM_INIT 0x02d 72*56818Sralph #define IMS332_REG_XFER_DELAY 0x02e 73*56818Sralph 74*56818Sralph #define IMS332_REG_COLOR_MASK 0x040 /* color mask register */ 75*56818Sralph 76*56818Sralph #define IMS332_REG_CSR_A 0x060 77*56818Sralph 78*56818Sralph #define IMS332_REG_CSR_B 0x070 79*56818Sralph 80*56818Sralph #define IMS332_REG_TOP_SCREEN 0x080 /* top-of-screen offset */ 81*56818Sralph 82*56818Sralph #define IMS332_REG_CURSOR_LUT_0 0x0a1 /* cursor palette */ 83*56818Sralph #define IMS332_REG_CURSOR_LUT_1 0x0a2 84*56818Sralph #define IMS332_REG_CURSOR_LUT_2 0x0a3 85*56818Sralph 86*56818Sralph #define IMS332_REG_RGB_CKSUM_0 0x0c0 /* test registers */ 87*56818Sralph #define IMS332_REG_RGB_CKSUM_1 0x0c1 88*56818Sralph #define IMS332_REG_RGB_CKSUM_2 0x0c2 89*56818Sralph 90*56818Sralph #define IMS332_REG_CURSOR_LOC 0x0c7 /* cursor location */ 91*56818Sralph 92*56818Sralph #define IMS332_REG_LUT_BASE 0x100 /* color palette */ 93*56818Sralph #define IMS332_REG_LUT_END 0x1ff 94*56818Sralph 95*56818Sralph #define IMS332_REG_CURSOR_RAM 0x200 /* cursor bitmap */ 96*56818Sralph #define IMS332_REG_CURSOR_RAM_END 0x3ff 97*56818Sralph 98*56818Sralph /* 99*56818Sralph * Control register A 100*56818Sralph */ 101*56818Sralph 102*56818Sralph #define IMS332_CSR_A_VTG_ENABLE 0x000001 /* vertical timing generator */ 103*56818Sralph #define IMS332_CSR_A_INTERLACED 0x000002 /* screen format */ 104*56818Sralph #define IMS332_CSR_A_CCIR 0x000004 /* default is EIA */ 105*56818Sralph #define IMS332_CSR_A_SLAVE_SYNC 0x000008 /* else from our pll */ 106*56818Sralph #define IMS332_CSR_A_PLAIN_SYNC 0x000010 /* else tesselated */ 107*56818Sralph #define IMS332_CSR_A_SEPARATE_SYNC 0x000020 /* else composite */ 108*56818Sralph #define IMS332_CSR_A_VIDEO_ONLY 0x000040 /* else video+sync */ 109*56818Sralph #define IMS332_CSR_A_BLANK_PEDESTAL 0x000080 /* blank level */ 110*56818Sralph #define IMS332_CSR_A_CBLANK_IS_OUT 0x000100 111*56818Sralph #define IMS332_CSR_A_CBLANK_NO_DELAY 0x000200 112*56818Sralph #define IMS332_CSR_A_FORCE_BLANK 0x000400 113*56818Sralph #define IMS332_CSR_A_BLANK_DISABLE 0x000800 114*56818Sralph #define IMS332_CSR_A_VRAM_INCREMENT 0x003000 115*56818Sralph # define IMS332_VRAM_INC_1 0x000000 116*56818Sralph # define IMS332_VRAM_INC_256 0x001000 /* except interlaced->2 */ 117*56818Sralph # define IMS332_VRAM_INC_512 0x002000 118*56818Sralph # define IMS332_VRAM_INC_1024 0x003000 119*56818Sralph #define IMS332_CSR_A_DMA_DISABLE 0x004000 120*56818Sralph #define IMS332_CSR_A_SYNC_DELAY_MASK 0x038000 /* 0-7 VTG clk delays */ 121*56818Sralph #define IMS332_CSR_A_PIXEL_INTERLEAVE 0x040000 122*56818Sralph #define IMS332_CSR_A_DELAYED_SAMPLING 0x080000 123*56818Sralph #define IMS332_CSR_A_BITS_PER_PIXEL 0x700000 124*56818Sralph # define IMS332_BPP_1 0x000000 125*56818Sralph # define IMS332_BPP_2 0x100000 126*56818Sralph # define IMS332_BPP_4 0x200000 127*56818Sralph # define IMS332_BPP_8 0x300000 128*56818Sralph # define IMS332_BPP_15 0x400000 129*56818Sralph # define IMS332_BPP_16 0x500000 130*56818Sralph #define IMS332_CSR_A_DISABLE_CURSOR 0x800000 131*56818Sralph 132*56818Sralph 133*56818Sralph /* 134*56818Sralph * Control register B is mbz 135*56818Sralph */ 136*56818Sralph 137*56818Sralph /* 138*56818Sralph * Boot register 139*56818Sralph */ 140*56818Sralph 141*56818Sralph #define IMS332_BOOT_PLL 0x00001f /* xPLL, binary */ 142*56818Sralph #define IMS332_BOOT_CLOCK_PLL 0x000020 /* else xternal */ 143*56818Sralph #define IMS332_BOOT_64_BIT_MODE 0x000040 /* else 32 */ 144*56818Sralph #define IMS332_BOOT_xxx 0xffff80 /* reserved, mbz */ 145