141051Swilliam /*- 241051Swilliam * Copyright (c) 1990 The Regents of the University of California. 341051Swilliam * All rights reserved. 441051Swilliam * 541051Swilliam * This code is derived from software contributed to Berkeley by 641051Swilliam * William Jolitz. 741051Swilliam * 849573Swilliam * %sccs.include.redist.c% 941051Swilliam * 10*55647Sbostic * @(#)isa.h 5.8 (Berkeley) 07/23/92 1141051Swilliam */ 1241051Swilliam 1341051Swilliam /* 1445527Sbill * ISA Bus conventions 1541051Swilliam */ 1645527Sbill 17*55647Sbostic /*#ifndef LOCORE 1845543Sbill unsigned char inb(), rtcin(); 1945543Sbill void outb(); 20*55647Sbostic #endif*/ 2141051Swilliam 22*55647Sbostic #ifndef LOCORE 23*55647Sbostic unsigned char rtcin(); 2441051Swilliam 25*55647Sbostic #define inb(io) ({u_short iop; register u_char rtn; \ 26*55647Sbostic iop = (io); \ 27*55647Sbostic asm (" movl %1,%%edx; inb %%al,%%dx; movzbl %%al,%0 " \ 28*55647Sbostic : "=r" (rtn) \ 29*55647Sbostic : "g" (iop) \ 30*55647Sbostic : "ax,dx"); \ 31*55647Sbostic rtn; \ 32*55647Sbostic }) 33*55647Sbostic 34*55647Sbostic #define outb(io, v) ({u_short iop; u_char val; \ 35*55647Sbostic iop = (io); \ 36*55647Sbostic val = (v); \ 37*55647Sbostic asm (" movl %1,%%edx; movl %0,%%eax; outb %%dx,%%al " \ 38*55647Sbostic : \ 39*55647Sbostic : "g" (val) \ 40*55647Sbostic : "g" (iop) \ 41*55647Sbostic : "ax,dx"); \ 42*55647Sbostic }) 43*55647Sbostic 44*55647Sbostic #endif 4545527Sbill /* 4645527Sbill * Input / Output Port Assignments 4745527Sbill */ 4841051Swilliam 4945527Sbill #ifndef IO_BEGIN 5045527Sbill #define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ 5141051Swilliam 5245527Sbill /* CPU Board */ 5345624Sbill #define IO_DMA1 0x000 /* 8237A DMA Controller #1 */ 5445624Sbill #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ 5545624Sbill #define IO_TIMER1 0x040 /* 8252 Timer #1 */ 5645624Sbill #define IO_TIMER2 0x048 /* 8252 Timer #2 */ 5745527Sbill #define IO_KBD 0x060 /* 8042 Keyboard */ 5845527Sbill #define IO_RTC 0x070 /* RTC */ 5945527Sbill #define IO_NMI IO_RTC /* NMI Control */ 6045527Sbill #define IO_DMAPG 0x080 /* DMA Page Registers */ 6145624Sbill #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ 6245624Sbill #define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */ 6345527Sbill #define IO_NPX 0x0F0 /* Numeric Coprocessor */ 6441051Swilliam 6545527Sbill /* Cards */ 6645527Sbill /* 0x100 - 0x16F Open */ 6741051Swilliam 6845624Sbill #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */ 6941051Swilliam 7045527Sbill /* 0x178 - 0x1EF Open */ 7141051Swilliam 7245624Sbill #define IO_WD1 0x1f0 /* Primary Fixed Disk Controller */ 7345527Sbill #define IO_GAME 0x200 /* Game Controller */ 7441051Swilliam 7545527Sbill /* 0x208 - 0x277 Open */ 7645526Sbill 7745624Sbill #define IO_LPT2 0x278 /* Parallel Port #2 */ 7845526Sbill 7945527Sbill /* 0x280 - 0x2F7 Open */ 8045527Sbill 8145624Sbill #define IO_COM2 0x2f8 /* COM2 i/o address */ 8245527Sbill 8345527Sbill /* 0x300 - 0x36F Open */ 8445527Sbill 8545624Sbill #define IO_FD2 0x370 /* secondary base i/o address */ 8645624Sbill #define IO_LPT1 0x378 /* Parallel Port #1 */ 8745527Sbill 8845527Sbill /* 0x380 - 0x3AF Open */ 8945527Sbill 9045527Sbill #define IO_MDA 0x3B0 /* Monochome Adapter */ 9145624Sbill #define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */ 9245527Sbill #define IO_VGA 0x3C0 /* E/VGA Ports */ 9345527Sbill #define IO_CGA 0x3D0 /* CGA Ports */ 9445527Sbill 9545527Sbill /* 0x3E0 - 0x3EF Open */ 9645527Sbill 9745624Sbill #define IO_FD1 0x3f0 /* primary base i/o address */ 9845624Sbill #define IO_COM1 0x3f8 /* COM1 i/o address */ 9945527Sbill 10045527Sbill #define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */ 10145527Sbill #endif IO_ISABEGIN 10245527Sbill 10345527Sbill /* 10445527Sbill * Input / Output Memory Physical Addresses 10545527Sbill */ 10645527Sbill 10745624Sbill #ifndef IOM_BEGIN 108*55647Sbostic #define IOM_BEGIN 0xa0000 /* Start of I/O Memory "hole" */ 109*55647Sbostic #define IOM_END 0xFFFFF /* End of I/O Memory "hole" */ 11045527Sbill #endif IOM_BEGIN 11145527Sbill 11245527Sbill /* 11345527Sbill * RAM Physical Address Space (ignoring the above mentioned "hole") 11445527Sbill */ 11545527Sbill 11645624Sbill #ifndef RAM_BEGIN 117*55647Sbostic #define RAM_BEGIN 0x000000 /* Start of RAM Memory */ 118*55647Sbostic #define RAM_END 0xFFFFFF /* End of RAM Memory */ 119*55647Sbostic #endif IOM_BEGIN 12045527Sbill 12145527Sbill /* 12245527Sbill * Oddball Physical Memory Addresses 12345527Sbill */ 12445624Sbill #ifndef COMPAQ_RAMRELOC 12545527Sbill #define COMPAQ_RAMRELOC 0x80c00000 /* Compaq RAM relocation/diag */ 12645527Sbill #define COMPAQ_RAMSETUP 0x80c00002 /* Compaq RAM setup */ 12745527Sbill #define WEITEK_FPU 0xC0000000 /* WTL 2167 */ 12845527Sbill #define CYRIX_EMC 0xC0000000 /* Cyrix EMC */ 12945624Sbill #endif COMPAQ_RAMRELOC 130