141051Swilliam /*- 241051Swilliam * Copyright (c) 1990 The Regents of the University of California. 341051Swilliam * All rights reserved. 441051Swilliam * 541051Swilliam * This code is derived from software contributed to Berkeley by 641051Swilliam * William Jolitz. 741051Swilliam * 841051Swilliam * %sccs.include.noredist.c% 941051Swilliam * 10*45624Sbill * @(#)isa.h 5.5 (Berkeley) 11/18/90 1141051Swilliam */ 1241051Swilliam 1341051Swilliam /* 1445527Sbill * ISA Bus conventions 1541051Swilliam */ 1645527Sbill 1745526Sbill #ifndef LOCORE 1845543Sbill unsigned char inb(), rtcin(); 1945543Sbill void outb(); 2045527Sbill #endif 2141051Swilliam 2241051Swilliam 2345527Sbill /* 2445527Sbill * Input / Output Port Assignments 2545527Sbill */ 2641051Swilliam 2745527Sbill #ifndef IO_BEGIN 2845527Sbill #define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ 2941051Swilliam 3045527Sbill /* CPU Board */ 31*45624Sbill #define IO_DMA1 0x000 /* 8237A DMA Controller #1 */ 32*45624Sbill #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ 33*45624Sbill #define IO_TIMER1 0x040 /* 8252 Timer #1 */ 34*45624Sbill #define IO_TIMER2 0x048 /* 8252 Timer #2 */ 3545527Sbill #define IO_KBD 0x060 /* 8042 Keyboard */ 3645527Sbill #define IO_RTC 0x070 /* RTC */ 3745527Sbill #define IO_NMI IO_RTC /* NMI Control */ 3845527Sbill #define IO_DMAPG 0x080 /* DMA Page Registers */ 39*45624Sbill #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ 40*45624Sbill #define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */ 4145527Sbill #define IO_NPX 0x0F0 /* Numeric Coprocessor */ 4241051Swilliam 4345527Sbill /* Cards */ 4445527Sbill /* 0x100 - 0x16F Open */ 4541051Swilliam 46*45624Sbill #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */ 4741051Swilliam 4845527Sbill /* 0x178 - 0x1EF Open */ 4941051Swilliam 50*45624Sbill #define IO_WD1 0x1f0 /* Primary Fixed Disk Controller */ 5145527Sbill #define IO_GAME 0x200 /* Game Controller */ 5241051Swilliam 5345527Sbill /* 0x208 - 0x277 Open */ 5445526Sbill 55*45624Sbill #define IO_LPT2 0x278 /* Parallel Port #2 */ 5645526Sbill 5745527Sbill /* 0x280 - 0x2F7 Open */ 5845527Sbill 59*45624Sbill #define IO_COM2 0x2f8 /* COM2 i/o address */ 6045527Sbill 6145527Sbill /* 0x300 - 0x36F Open */ 6245527Sbill 63*45624Sbill #define IO_FD2 0x370 /* secondary base i/o address */ 64*45624Sbill #define IO_LPT1 0x378 /* Parallel Port #1 */ 6545527Sbill 6645527Sbill /* 0x380 - 0x3AF Open */ 6745527Sbill 6845527Sbill #define IO_MDA 0x3B0 /* Monochome Adapter */ 69*45624Sbill #define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */ 7045527Sbill #define IO_VGA 0x3C0 /* E/VGA Ports */ 7145527Sbill #define IO_CGA 0x3D0 /* CGA Ports */ 7245527Sbill 7345527Sbill /* 0x3E0 - 0x3EF Open */ 7445527Sbill 75*45624Sbill #define IO_FD1 0x3f0 /* primary base i/o address */ 76*45624Sbill #define IO_COM1 0x3f8 /* COM1 i/o address */ 7745527Sbill 7845527Sbill #define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */ 7945527Sbill #endif IO_ISABEGIN 8045527Sbill 8145527Sbill /* 8245527Sbill * Input / Output Memory Physical Addresses 8345527Sbill */ 8445527Sbill 85*45624Sbill #ifndef IOM_BEGIN 8645527Sbill #define IOM_BEGIN 0xa0000 /* Start of I/O Memory "hole" */ 8745527Sbill #define IOM_END 0xFFFFF /* End of I/O Memory "hole" */ 8845527Sbill #endif IOM_BEGIN 8945527Sbill 9045527Sbill /* 9145527Sbill * RAM Physical Address Space (ignoring the above mentioned "hole") 9245527Sbill */ 9345527Sbill 94*45624Sbill #ifndef RAM_BEGIN 9545527Sbill #define RAM_BEGIN 0x000000 /* Start of RAM Memory */ 96*45624Sbill #define RAM_END 0xFFFFFF /* End of RAM Memory */ 9745527Sbill #endif IOM_BEGIN 9845527Sbill 9945527Sbill /* 10045527Sbill * Oddball Physical Memory Addresses 10145527Sbill */ 102*45624Sbill #ifndef COMPAQ_RAMRELOC 10345527Sbill #define COMPAQ_RAMRELOC 0x80c00000 /* Compaq RAM relocation/diag */ 10445527Sbill #define COMPAQ_RAMSETUP 0x80c00002 /* Compaq RAM setup */ 10545527Sbill #define WEITEK_FPU 0xC0000000 /* WTL 2167 */ 10645527Sbill #define CYRIX_EMC 0xC0000000 /* Cyrix EMC */ 107*45624Sbill #endif COMPAQ_RAMRELOC 108