141051Swilliam /*- 241051Swilliam * Copyright (c) 1990 The Regents of the University of California. 341051Swilliam * All rights reserved. 441051Swilliam * 541051Swilliam * This code is derived from software contributed to Berkeley by 641051Swilliam * William Jolitz. 741051Swilliam * 841051Swilliam * %sccs.include.noredist.c% 941051Swilliam * 10*45527Sbill * @(#)isa.h 5.3 (Berkeley) 11/07/90 1141051Swilliam */ 1241051Swilliam 1341051Swilliam /* 14*45527Sbill * ISA Bus conventions 1541051Swilliam */ 16*45527Sbill 1745526Sbill #ifndef LOCORE 18*45527Sbill unsigned char inb() ; /* XXX */ 19*45527Sbill extern outb(); 20*45527Sbill #endif 2141051Swilliam 2241051Swilliam 23*45527Sbill /* 24*45527Sbill * Input / Output Port Assignments 25*45527Sbill */ 2641051Swilliam 27*45527Sbill #ifndef IO_BEGIN 28*45527Sbill #define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ 2941051Swilliam 30*45527Sbill /* CPU Board */ 31*45527Sbill #define IO_DMA0 0x000 /* 8237A DMA Controller #1 */ 32*45527Sbill #define IO_ICU0 0x020 /* 8259A Interrupt Controller #1 */ 33*45527Sbill #define IO_TIMER0 0x040 /* 8252 Timer #1 */ 34*45527Sbill #define IO_TIMER1 0x048 /* 8252 Timer #2 */ 35*45527Sbill #define IO_KBD 0x060 /* 8042 Keyboard */ 36*45527Sbill #define IO_RTC 0x070 /* RTC */ 37*45527Sbill #define IO_NMI IO_RTC /* NMI Control */ 38*45527Sbill #define IO_DMAPG 0x080 /* DMA Page Registers */ 39*45527Sbill #define IO_ICU1 0x0A0 /* 8259A Interrupt Controller #2 */ 40*45527Sbill #define IO_DMA1 0x0C0 /* 8237A DMA Controller #2 */ 41*45527Sbill #define IO_NPX 0x0F0 /* Numeric Coprocessor */ 4241051Swilliam 43*45527Sbill /* Cards */ 44*45527Sbill /* 0x100 - 0x16F Open */ 4541051Swilliam 46*45527Sbill #define IO_WD1 0x170 /* Secondary Fixed Disk Controller */ 4741051Swilliam 48*45527Sbill /* 0x178 - 0x1EF Open */ 4941051Swilliam 50*45527Sbill #define IO_WD0 0x1f0 /* Primary Fixed Disk Controller */ 51*45527Sbill #define IO_GAME 0x200 /* Game Controller */ 5241051Swilliam 53*45527Sbill /* 0x208 - 0x277 Open */ 5445526Sbill 55*45527Sbill #define IO_LPT1 0x278 /* Parallel Port #2 */ 5645526Sbill 57*45527Sbill /* 0x280 - 0x2F7 Open */ 58*45527Sbill 59*45527Sbill #define IO_COM1 0x2f8 /* COM2 i/o address */ 60*45527Sbill 61*45527Sbill /* 0x300 - 0x36F Open */ 62*45527Sbill 63*45527Sbill #define IO_FD1 0x370 /* secondary base i/o address */ 64*45527Sbill #define IO_LPT0 0x378 /* Parallel Port #1 */ 65*45527Sbill 66*45527Sbill /* 0x380 - 0x3AF Open */ 67*45527Sbill 68*45527Sbill #define IO_MDA 0x3B0 /* Monochome Adapter */ 69*45527Sbill #define IO_LPT2 0x3BC /* Monochome Adapter Printer Port */ 70*45527Sbill #define IO_VGA 0x3C0 /* E/VGA Ports */ 71*45527Sbill #define IO_CGA 0x3D0 /* CGA Ports */ 72*45527Sbill 73*45527Sbill /* 0x3E0 - 0x3EF Open */ 74*45527Sbill 75*45527Sbill #define IO_FD0 0x3f0 /* primary base i/o address */ 76*45527Sbill #define IO_COM0 0x3f8 /* COM1 i/o address */ 77*45527Sbill 78*45527Sbill #define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */ 79*45527Sbill #endif IO_ISABEGIN 80*45527Sbill 81*45527Sbill /* 82*45527Sbill * Input / Output Memory Physical Addresses 83*45527Sbill */ 84*45527Sbill 85*45527Sbill #ifdef IOM_BEGIN 86*45527Sbill #define IOM_BEGIN 0xa0000 /* Start of I/O Memory "hole" */ 87*45527Sbill #define IOM_END 0xFFFFF /* End of I/O Memory "hole" */ 88*45527Sbill #endif IOM_BEGIN 89*45527Sbill 90*45527Sbill /* 91*45527Sbill * RAM Physical Address Space (ignoring the above mentioned "hole") 92*45527Sbill */ 93*45527Sbill 94*45527Sbill #ifdef RAM_BEGIN 95*45527Sbill #define RAM_BEGIN 0x000000 /* Start of RAM Memory */ 96*45527Sbill #define IOM_END 0xFFFFFF /* End of RAM Memory */ 97*45527Sbill #endif IOM_BEGIN 98*45527Sbill 99*45527Sbill /* 100*45527Sbill * Oddball Physical Memory Addresses 101*45527Sbill */ 102*45527Sbill 103*45527Sbill #define COMPAQ_RAMRELOC 0x80c00000 /* Compaq RAM relocation/diag */ 104*45527Sbill #define COMPAQ_RAMSETUP 0x80c00002 /* Compaq RAM setup */ 105*45527Sbill #define WEITEK_FPU 0xC0000000 /* WTL 2167 */ 106*45527Sbill #define CYRIX_EMC 0xC0000000 /* Cyrix EMC */ 107