141054Swilliam /*- 241054Swilliam * Copyright (c) 1990 The Regents of the University of California. 341054Swilliam * All rights reserved. 441054Swilliam * 541054Swilliam * This code is derived from software contributed to Berkeley by 641054Swilliam * William Jolitz. 741054Swilliam * 8*49597Swilliam * %sccs.include.redist.c% 941054Swilliam * 10*49597Swilliam * @(#)icu.h 5.6 (Berkeley) 05/09/91 1141054Swilliam */ 1241054Swilliam 1341054Swilliam /* 1441054Swilliam * AT/386 Interrupt Control constants 1541054Swilliam * W. Jolitz 8/89 1641054Swilliam */ 1741054Swilliam 1843593Sdonahn #ifndef __ICU__ 1943593Sdonahn #define __ICU__ 2043593Sdonahn 2141054Swilliam #ifndef LOCORE 2245624Sbill 2345624Sbill /* 2445624Sbill * Interrupt "level" mechanism variables, masks, and macros 2545624Sbill */ 2641054Swilliam extern unsigned short imen; /* interrupt mask enable */ 2745624Sbill extern unsigned short cpl; /* current priority level mask */ 2841054Swilliam 2945624Sbill extern unsigned short highmask; /* group of interrupts masked with splhigh() */ 3045624Sbill extern unsigned short ttymask; /* group of interrupts masked with spltty() */ 3145624Sbill extern unsigned short biomask; /* group of interrupts masked with splbio() */ 3245624Sbill extern unsigned short netmask; /* group of interrupts masked with splimp() */ 3343593Sdonahn 3441054Swilliam #define INTREN(s) imen &= ~(s) 3541054Swilliam #define INTRDIS(s) imen |= (s) 3645544Sbill #define INTRMASK(msk,s) msk |= (s) 3745624Sbill 3845624Sbill #else 3945624Sbill 4045624Sbill /* 4145624Sbill * Macro's for interrupt level priority masks (used in interrupt vector entry) 4245624Sbill */ 4345624Sbill 4445624Sbill /* Mask a group of interrupts atomically */ 45*49597Swilliam #define INTR(unit,mask,offst) \ 4645624Sbill pushl $0 ; \ 4745624Sbill pushl $ T_ASTFLT ; \ 4845624Sbill pushal ; \ 4945624Sbill push %ds ; \ 5045624Sbill push %es ; \ 5145624Sbill movw $0x10, %ax ; \ 5245624Sbill movw %ax, %ds ; \ 5345624Sbill movw %ax,%es ; \ 5445624Sbill incl _cnt+V_INTR ; \ 55*49597Swilliam incl _isa_intr + offst * 4 ; \ 5645624Sbill movzwl _cpl,%eax ; \ 5745624Sbill pushl %eax ; \ 58*49597Swilliam pushl $ unit ; \ 59*49597Swilliam orw mask ,%ax ; \ 6045624Sbill movw %ax,_cpl ; \ 6145624Sbill orw _imen,%ax ; \ 6245624Sbill NOP ; \ 6345624Sbill outb %al,$ IO_ICU1+1 ; \ 6445624Sbill NOP ; \ 6545624Sbill movb %ah,%al ; \ 6645624Sbill outb %al,$ IO_ICU2+1 ; \ 6745624Sbill NOP ; \ 68*49597Swilliam inb $0x84,%al ; \ 6945624Sbill sti 7045624Sbill 7145624Sbill /* Interrupt vector exit macros */ 7245624Sbill 7345624Sbill /* First eight interrupts (ICU1) */ 74*49597Swilliam #define INTREXIT1 \ 7545624Sbill movb $0x20,%al ; \ 7645624Sbill outb %al,$ IO_ICU1 ; \ 7745624Sbill jmp doreti 7845624Sbill 7945624Sbill /* Second eight interrupts (ICU2) */ 80*49597Swilliam #define INTREXIT2 \ 8145624Sbill movb $0x20,%al ; \ 8245624Sbill outb %al,$ IO_ICU1 ; \ 8345624Sbill outb %al,$ IO_ICU2 ; \ 8445624Sbill jmp doreti 8545624Sbill 8641054Swilliam #endif 8741054Swilliam 8845624Sbill /* 8945624Sbill * Interrupt enable bits -- in order of priority 9045624Sbill */ 9145544Sbill #define IRQ0 0x0001 /* highest priority - timer */ 9245544Sbill #define IRQ1 0x0002 9345544Sbill #define IRQ_SLAVE 0x0004 9445544Sbill #define IRQ8 0x0100 9545544Sbill #define IRQ9 0x0200 9645544Sbill #define IRQ2 IRQ9 9745544Sbill #define IRQ10 0x0400 9845544Sbill #define IRQ11 0x0800 9945544Sbill #define IRQ12 0x1000 10045544Sbill #define IRQ13 0x2000 10145544Sbill #define IRQ14 0x4000 10245544Sbill #define IRQ15 0x8000 10345544Sbill #define IRQ3 0x0008 10445544Sbill #define IRQ4 0x0010 10545544Sbill #define IRQ5 0x0020 10645544Sbill #define IRQ6 0x0040 10745544Sbill #define IRQ7 0x0080 /* lowest - parallel printer */ 10841054Swilliam 10945624Sbill /* 11045624Sbill * Interrupt Control offset into Interrupt descriptor table (IDT) 11145624Sbill */ 11245624Sbill #define ICU_OFFSET 32 /* 0-31 are processor exceptions */ 11345624Sbill #define ICU_LEN 16 /* 32-47 are ISA interrupts */ 11445624Sbill 11543593Sdonahn #endif __ICU__ 116