141054Swilliam /*- 241054Swilliam * Copyright (c) 1990 The Regents of the University of California. 341054Swilliam * All rights reserved. 441054Swilliam * 541054Swilliam * This code is derived from software contributed to Berkeley by 641054Swilliam * William Jolitz. 741054Swilliam * 841054Swilliam * %sccs.include.386.c% 941054Swilliam * 10*45624Sbill * @(#)icu.h 5.4 (Berkeley) 11/18/90 1141054Swilliam */ 1241054Swilliam 1341054Swilliam /* 1441054Swilliam * AT/386 Interrupt Control constants 1541054Swilliam * W. Jolitz 8/89 1641054Swilliam */ 1741054Swilliam 1843593Sdonahn #ifndef __ICU__ 1943593Sdonahn #define __ICU__ 2043593Sdonahn 2141054Swilliam #ifndef LOCORE 22*45624Sbill 23*45624Sbill /* 24*45624Sbill * Interrupt "level" mechanism variables, masks, and macros 25*45624Sbill */ 2641054Swilliam extern unsigned short imen; /* interrupt mask enable */ 27*45624Sbill extern unsigned short cpl; /* current priority level mask */ 2841054Swilliam 29*45624Sbill extern unsigned short highmask; /* group of interrupts masked with splhigh() */ 30*45624Sbill extern unsigned short ttymask; /* group of interrupts masked with spltty() */ 31*45624Sbill extern unsigned short biomask; /* group of interrupts masked with splbio() */ 32*45624Sbill extern unsigned short netmask; /* group of interrupts masked with splimp() */ 3343593Sdonahn 3441054Swilliam #define INTREN(s) imen &= ~(s) 3541054Swilliam #define INTRDIS(s) imen |= (s) 3645544Sbill #define INTRMASK(msk,s) msk |= (s) 37*45624Sbill 38*45624Sbill #else 39*45624Sbill 40*45624Sbill /* 41*45624Sbill * Macro's for interrupt level priority masks (used in interrupt vector entry) 42*45624Sbill */ 43*45624Sbill 44*45624Sbill /* Just mask this interrupt only */ 45*45624Sbill #define INTR(a) \ 46*45624Sbill pushl $0 ; \ 47*45624Sbill pushl $ T_ASTFLT ; \ 48*45624Sbill pushal ; \ 49*45624Sbill push %ds ; \ 50*45624Sbill push %es ; \ 51*45624Sbill movw $0x10, %ax ; \ 52*45624Sbill movw %ax, %ds ; \ 53*45624Sbill movw %ax,%es ; \ 54*45624Sbill incl _cnt+V_INTR ; \ 55*45624Sbill movzwl _cpl,%eax ; \ 56*45624Sbill pushl %eax ; \ 57*45624Sbill pushl $ a ; \ 58*45624Sbill orw $ IRQ/**/a ,%ax ; \ 59*45624Sbill movw %ax,_cpl ; \ 60*45624Sbill orw _imen,%ax ; \ 61*45624Sbill NOP ; \ 62*45624Sbill outb %al,$ IO_ICU1+1 ; \ 63*45624Sbill NOP ; \ 64*45624Sbill movb %ah,%al ; \ 65*45624Sbill outb %al,$ IO_ICU2+1 ; \ 66*45624Sbill NOP ; \ 67*45624Sbill sti 68*45624Sbill 69*45624Sbill /* Mask a group of interrupts atomically */ 70*45624Sbill #define INTRN(a,b) \ 71*45624Sbill pushl $0 ; \ 72*45624Sbill pushl $ T_ASTFLT ; \ 73*45624Sbill pushal ; \ 74*45624Sbill push %ds ; \ 75*45624Sbill push %es ; \ 76*45624Sbill movw $0x10, %ax ; \ 77*45624Sbill movw %ax, %ds ; \ 78*45624Sbill movw %ax,%es ; \ 79*45624Sbill incl _cnt+V_INTR ; \ 80*45624Sbill movzwl _cpl,%eax ; \ 81*45624Sbill pushl %eax ; \ 82*45624Sbill pushl $ a ; \ 83*45624Sbill orw $ IRQ/**/a ,%ax ; \ 84*45624Sbill orw b ,%ax ; \ 85*45624Sbill movw %ax,_cpl ; \ 86*45624Sbill orw _imen,%ax ; \ 87*45624Sbill NOP ; \ 88*45624Sbill outb %al,$ IO_ICU1+1 ; \ 89*45624Sbill NOP ; \ 90*45624Sbill movb %ah,%al ; \ 91*45624Sbill outb %al,$ IO_ICU2+1 ; \ 92*45624Sbill NOP ; \ 93*45624Sbill sti 94*45624Sbill 95*45624Sbill /* Interrupt vector exit macros */ 96*45624Sbill 97*45624Sbill /* First eight interrupts (ICU1) */ 98*45624Sbill #define INTREXT1 \ 99*45624Sbill movb $0x20,%al ; \ 100*45624Sbill outb %al,$ IO_ICU1 ; \ 101*45624Sbill jmp doreti 102*45624Sbill 103*45624Sbill /* Second eight interrupts (ICU2) */ 104*45624Sbill #define INTREXT2 \ 105*45624Sbill movb $0x20,%al ; \ 106*45624Sbill outb %al,$ IO_ICU1 ; \ 107*45624Sbill outb %al,$ IO_ICU2 ; \ 108*45624Sbill jmp doreti 109*45624Sbill 11041054Swilliam #endif 11141054Swilliam 112*45624Sbill /* 113*45624Sbill * Interrupt enable bits -- in order of priority 114*45624Sbill */ 11545544Sbill #define IRQ0 0x0001 /* highest priority - timer */ 11645544Sbill #define IRQ1 0x0002 11745544Sbill #define IRQ_SLAVE 0x0004 11845544Sbill #define IRQ8 0x0100 11945544Sbill #define IRQ9 0x0200 12045544Sbill #define IRQ2 IRQ9 12145544Sbill #define IRQ10 0x0400 12245544Sbill #define IRQ11 0x0800 12345544Sbill #define IRQ12 0x1000 12445544Sbill #define IRQ13 0x2000 12545544Sbill #define IRQ14 0x4000 12645544Sbill #define IRQ15 0x8000 12745544Sbill #define IRQ3 0x0008 12845544Sbill #define IRQ4 0x0010 12945544Sbill #define IRQ5 0x0020 13045544Sbill #define IRQ6 0x0040 13145544Sbill #define IRQ7 0x0080 /* lowest - parallel printer */ 13241054Swilliam 133*45624Sbill /* 134*45624Sbill * Interrupt Control offset into Interrupt descriptor table (IDT) 135*45624Sbill */ 136*45624Sbill #define ICU_OFFSET 32 /* 0-31 are processor exceptions */ 137*45624Sbill #define ICU_LEN 16 /* 32-47 are ISA interrupts */ 138*45624Sbill 13943593Sdonahn #endif __ICU__ 140