147753Swilliam /*- 2*49571Swilliam * Copyright (c) 1991 The Regents of the University of California. 3*49571Swilliam * All rights reserved. 447753Swilliam * 547753Swilliam * %sccs.include.redist.c% 647753Swilliam * 7*49571Swilliam * @(#)comreg.h 7.2 (Berkeley) 05/09/91 847753Swilliam */ 947753Swilliam 1047753Swilliam 1147753Swilliam /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ 1247753Swilliam #define COMBRD(x) (1843200 / (16*(x))) 1347753Swilliam 1447753Swilliam /* interrupt enable register */ 1547753Swilliam #define IER_ERXRDY 0x1 1647753Swilliam #define IER_ETXRDY 0x2 1747753Swilliam #define IER_ERLS 0x4 1847753Swilliam #define IER_EMSC 0x8 1947753Swilliam 2047753Swilliam /* interrupt identification register */ 21*49571Swilliam #define IIR_IMASK 0xf 22*49571Swilliam #define IIR_RXTOUT 0xc 23*49571Swilliam #define IIR_RLS 0x6 24*49571Swilliam #define IIR_RXRDY 0x4 25*49571Swilliam #define IIR_TXRDY 0x2 2647753Swilliam #define IIR_NOPEND 0x1 27*49571Swilliam #define IIR_MLSC 0x0 28*49571Swilliam #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 2947753Swilliam 30*49571Swilliam /* fifo control register */ 31*49571Swilliam #define FIFO_ENABLE 0x01 32*49571Swilliam #define FIFO_RCV_RST 0x02 33*49571Swilliam #define FIFO_XMT_RST 0x04 34*49571Swilliam #define FIFO_DMA_MODE 0x08 35*49571Swilliam #define FIFO_TRIGGER_1 0x00 36*49571Swilliam #define FIFO_TRIGGER_4 0x40 37*49571Swilliam #define FIFO_TRIGGER_8 0x80 38*49571Swilliam #define FIFO_TRIGGER_14 0xc0 39*49571Swilliam 4047753Swilliam /* character format control register */ 4147753Swilliam #define CFCR_DLAB 0x80 4247753Swilliam #define CFCR_SBREAK 0x40 4347753Swilliam #define CFCR_PZERO 0x30 4447753Swilliam #define CFCR_PONE 0x20 4547753Swilliam #define CFCR_PEVEN 0x10 4647753Swilliam #define CFCR_PODD 0x00 4747753Swilliam #define CFCR_PENAB 0x08 4847753Swilliam #define CFCR_STOPB 0x04 4947753Swilliam #define CFCR_8BITS 0x03 5047753Swilliam #define CFCR_7BITS 0x02 5147753Swilliam #define CFCR_6BITS 0x01 5247753Swilliam #define CFCR_5BITS 0x00 5347753Swilliam 5447753Swilliam /* modem control register */ 5547753Swilliam #define MCR_LOOPBACK 0x10 5647753Swilliam #define MCR_IENABLE 0x08 5747753Swilliam #define MCR_DRS 0x04 5847753Swilliam #define MCR_RTS 0x02 5947753Swilliam #define MCR_DTR 0x01 6047753Swilliam 6147753Swilliam /* line status register */ 62*49571Swilliam #define LSR_RCV_FIFO 0x80 6347753Swilliam #define LSR_TSRE 0x40 6447753Swilliam #define LSR_TXRDY 0x20 6547753Swilliam #define LSR_BI 0x10 6647753Swilliam #define LSR_FE 0x08 6747753Swilliam #define LSR_PE 0x04 6847753Swilliam #define LSR_OE 0x02 6947753Swilliam #define LSR_RXRDY 0x01 70*49571Swilliam #define LSR_RCV_MASK 0x1f 7147753Swilliam 7247753Swilliam /* modem status register */ 7347753Swilliam #define MSR_DCD 0x80 7447753Swilliam #define MSR_RI 0x40 7547753Swilliam #define MSR_DSR 0x20 7647753Swilliam #define MSR_CTS 0x10 7747753Swilliam #define MSR_DDCD 0x08 7847753Swilliam #define MSR_TERI 0x04 7947753Swilliam #define MSR_DDSR 0x02 8047753Swilliam #define MSR_DCTS 0x01 8147753Swilliam 82*49571Swilliam /* 83*49571Swilliam * WARNING: Serial console is assumed to be at COM1 address 84*49571Swilliam * and CONUNIT must be 0. 85*49571Swilliam */ 86*49571Swilliam #define CONADDR (0x3f8) 87*49571Swilliam #define CONUNIT (0) 88