1*47753Swilliam /*- 2*47753Swilliam * Copyright (c) 1982, 1986, 1990, 1991 The Regents of the University of 3*47753Swilliam * California. All rights reserved. 4*47753Swilliam * 5*47753Swilliam * This code is derived from software contributed to Berkeley by 6*47753Swilliam * the University of Utah and William Jolitz. 7*47753Swilliam * 8*47753Swilliam * %sccs.include.redist.c% 9*47753Swilliam * 10*47753Swilliam * @(#)comreg.h 7.1 (Berkeley) 04/03/91 11*47753Swilliam */ 12*47753Swilliam 13*47753Swilliam 14*47753Swilliam /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ 15*47753Swilliam #define COMBRD(x) (1843200 / (16*(x))) 16*47753Swilliam 17*47753Swilliam /* interrupt enable register */ 18*47753Swilliam #define IER_ERXRDY 0x1 19*47753Swilliam #define IER_ETXRDY 0x2 20*47753Swilliam #define IER_ERLS 0x4 21*47753Swilliam #define IER_EMSC 0x8 22*47753Swilliam 23*47753Swilliam /* interrupt identification register */ 24*47753Swilliam #define IIR_NOPEND 0x1 25*47753Swilliam #define IIR_IMASK 0x6 26*47753Swilliam #define IIR_RLS 6 27*47753Swilliam #define IIR_RXRDY 4 28*47753Swilliam #define IIR_TXRDY 2 29*47753Swilliam #define IIR_MLSC 0 30*47753Swilliam 31*47753Swilliam /* character format control register */ 32*47753Swilliam #define CFCR_DLAB 0x80 33*47753Swilliam #define CFCR_SBREAK 0x40 34*47753Swilliam #define CFCR_PZERO 0x30 35*47753Swilliam #define CFCR_PONE 0x20 36*47753Swilliam #define CFCR_PEVEN 0x10 37*47753Swilliam #define CFCR_PODD 0x00 38*47753Swilliam #define CFCR_PENAB 0x08 39*47753Swilliam #define CFCR_STOPB 0x04 40*47753Swilliam #define CFCR_8BITS 0x03 41*47753Swilliam #define CFCR_7BITS 0x02 42*47753Swilliam #define CFCR_6BITS 0x01 43*47753Swilliam #define CFCR_5BITS 0x00 44*47753Swilliam 45*47753Swilliam /* modem control register */ 46*47753Swilliam #define MCR_LOOPBACK 0x10 47*47753Swilliam #define MCR_IENABLE 0x08 48*47753Swilliam #define MCR_DRS 0x04 49*47753Swilliam #define MCR_RTS 0x02 50*47753Swilliam #define MCR_DTR 0x01 51*47753Swilliam 52*47753Swilliam /* line status register */ 53*47753Swilliam #define LSR_TSRE 0x40 54*47753Swilliam #define LSR_TXRDY 0x20 55*47753Swilliam #define LSR_BI 0x10 56*47753Swilliam #define LSR_FE 0x08 57*47753Swilliam #define LSR_PE 0x04 58*47753Swilliam #define LSR_OE 0x02 59*47753Swilliam #define LSR_RXRDY 0x01 60*47753Swilliam 61*47753Swilliam /* modem status register */ 62*47753Swilliam #define MSR_DCD 0x80 63*47753Swilliam #define MSR_RI 0x40 64*47753Swilliam #define MSR_DSR 0x20 65*47753Swilliam #define MSR_CTS 0x10 66*47753Swilliam #define MSR_DDCD 0x08 67*47753Swilliam #define MSR_TERI 0x04 68*47753Swilliam #define MSR_DDSR 0x02 69*47753Swilliam #define MSR_DCTS 0x01 70*47753Swilliam 71