1*41480Smckusick /* 2*41480Smckusick * Copyright (c) 1988 University of Utah. 3*41480Smckusick * Copyright (c) 1990 The Regents of the University of California. 4*41480Smckusick * All rights reserved. 5*41480Smckusick * 6*41480Smckusick * This code is derived from software contributed to Berkeley by 7*41480Smckusick * the Systems Programming Group of the University of Utah Computer 8*41480Smckusick * Science Department. 9*41480Smckusick * 10*41480Smckusick * %sccs.include.redist.c% 11*41480Smckusick * 12*41480Smckusick * from: Utah $Hdr: grf_rbreg.h 1.8 89/08/25$ 13*41480Smckusick * 14*41480Smckusick * @(#)grf_rbreg.h 7.1 (Berkeley) 05/08/90 15*41480Smckusick */ 16*41480Smckusick 17*41480Smckusick /* 18*41480Smckusick * Map of the Renaissance frame buffer controller chip in memory ... 19*41480Smckusick */ 20*41480Smckusick 21*41480Smckusick #define rb_waitbusy(regaddr) \ 22*41480Smckusick while (((struct rboxfb *)(regaddr))->wbusy & 0x01) DELAY(100) 23*41480Smckusick 24*41480Smckusick #define CM1RED ((struct rencm *)(ip->regbase + 0x6400)) 25*41480Smckusick #define CM1GRN ((struct rencm *)(ip->regbase + 0x6800)) 26*41480Smckusick #define CM1BLU ((struct rencm *)(ip->regbase + 0x6C00)) 27*41480Smckusick #define CM2RED ((struct rencm *)(ip->regbase + 0x7400)) 28*41480Smckusick #define CM2GRN ((struct rencm *)(ip->regbase + 0x7800)) 29*41480Smckusick #define CM2BLU ((struct rencm *)(ip->regbase + 0x7C00)) 30*41480Smckusick 31*41480Smckusick #define vu_char volatile u_char 32*41480Smckusick #define vu_short volatile u_short 33*41480Smckusick #define vu_int volatile u_int 34*41480Smckusick 35*41480Smckusick struct rencm { 36*41480Smckusick u_char :8, :8, :8; 37*41480Smckusick vu_char value; 38*41480Smckusick }; 39*41480Smckusick 40*41480Smckusick struct rboxfb { 41*41480Smckusick u_char filler1[1]; 42*41480Smckusick vu_char reset; /* reset register 0x01 */ 43*41480Smckusick vu_char fb_address; /* frame buffer address 0x02 */ 44*41480Smckusick vu_char interrupt; /* interrupt register 0x03 */ 45*41480Smckusick u_char filler1a; 46*41480Smckusick vu_char fbwmsb; /* frame buffer width MSB 0x05 */ 47*41480Smckusick u_char filler1b; 48*41480Smckusick vu_char fbwlsb; /* frame buffer width MSB 0x07 */ 49*41480Smckusick u_char filler1c; 50*41480Smckusick vu_char fbhmsb; /* frame buffer height MSB 0x09 */ 51*41480Smckusick u_char filler1d; 52*41480Smckusick vu_char fbhlsb; /* frame buffer height MSB 0x0b */ 53*41480Smckusick u_char filler1e; 54*41480Smckusick vu_char dwmsb; /* display width MSB 0x0d */ 55*41480Smckusick u_char filler1f; 56*41480Smckusick vu_char dwlsb; /* display width MSB 0x0f */ 57*41480Smckusick u_char filler1g; 58*41480Smckusick vu_char dhmsb; /* display height MSB 0x11 */ 59*41480Smckusick u_char filler1h; 60*41480Smckusick vu_char dhlsb; /* display height MSB 0x13 */ 61*41480Smckusick u_char filler1i; 62*41480Smckusick vu_char fbid; /* frame buffer id 0x15 */ 63*41480Smckusick u_char filler1j[0x47]; 64*41480Smckusick vu_char fbomsb; /* frame buffer offset MSB 0x5d */ 65*41480Smckusick u_char filler1k; 66*41480Smckusick vu_char fbolsb; /* frame buffer offset LSB 0x5f */ 67*41480Smckusick u_char filler2[16359]; 68*41480Smckusick vu_char wbusy; /* window mover is active 0x4047 */ 69*41480Smckusick u_char filler3[0x405b - 0x4048]; 70*41480Smckusick vu_char scanbusy; /* scan converteris active 0x405B */ 71*41480Smckusick u_char filler3b[0x4083 - 0x405c]; 72*41480Smckusick vu_char video_enable; /* drive vid. refresh bus 0x4083 */ 73*41480Smckusick u_char filler4[3]; 74*41480Smckusick vu_char display_enable; /* enable the display 0x4087 */ 75*41480Smckusick u_char filler5[8]; 76*41480Smckusick vu_int write_enable; /* write enable register 0x4090 */ 77*41480Smckusick u_char filler6[11]; 78*41480Smckusick vu_char wmove; /* start window mover 0x409f */ 79*41480Smckusick u_char filler7[3]; 80*41480Smckusick vu_char blink; /* blink register 0x40a3 */ 81*41480Smckusick u_char filler8[15]; 82*41480Smckusick vu_char fold; /* fold register 0x40b3 */ 83*41480Smckusick vu_int opwen; /* overlay plane write enable 0x40b4 */ 84*41480Smckusick u_char filler9[3]; 85*41480Smckusick vu_char tmode; /* Tile mode size 0x40bb */ 86*41480Smckusick u_char filler9a[3]; 87*41480Smckusick vu_char drive; /* drive register 0x40bf */ 88*41480Smckusick u_char filler10[3]; 89*41480Smckusick vu_char vdrive; /* vdrive register 0x40c3 */ 90*41480Smckusick u_char filler10a[0x40cb-0x40c4]; 91*41480Smckusick vu_char zconfig; /* Z-buffer mode 0x40cb */ 92*41480Smckusick u_char filler11a[2]; 93*41480Smckusick vu_short tpatt; /* Transparency pattern 0x40ce */ 94*41480Smckusick u_char filler11b[3]; 95*41480Smckusick vu_char dmode; /* dither mode 0x40d3 */ 96*41480Smckusick u_char filler11c[3]; 97*41480Smckusick vu_char en_scan; /* enable scan board to DTACK 0x40d7 */ 98*41480Smckusick u_char filler11d[0x40ef-0x40d8]; 99*41480Smckusick vu_char rep_rule; /* replacement rule 0x40ef */ 100*41480Smckusick u_char filler12[2]; 101*41480Smckusick vu_short source_x; /* source x 0x40f2 */ 102*41480Smckusick u_char filler13[2]; 103*41480Smckusick vu_short source_y; /* source y 0x40f6 */ 104*41480Smckusick u_char filler14[2]; 105*41480Smckusick vu_short dest_x; /* dest x 0x40fa */ 106*41480Smckusick u_char filler15[2]; 107*41480Smckusick vu_short dest_y; /* dest y 0x40fe */ 108*41480Smckusick u_char filler16[2]; 109*41480Smckusick vu_short wwidth; /* window width 0x4102 */ 110*41480Smckusick u_char filler17[2]; 111*41480Smckusick vu_short wheight; /* window height 0x4106 */ 112*41480Smckusick u_char filler18[18]; 113*41480Smckusick vu_short patt_x; /* pattern x 0x411a */ 114*41480Smckusick u_char filler19[2]; 115*41480Smckusick vu_short patt_y; /* pattern y 0x411e */ 116*41480Smckusick u_char filler20[0x8012 - 0x4120]; 117*41480Smckusick vu_short te_status; /* transform engine status 0x8012 */ 118*41480Smckusick u_char filler21[0x1ffff-0x8014]; 119*41480Smckusick }; 120