1*41480Smckusick /* 2*41480Smckusick * Copyright (c) 1982, 1990 The Regents of the University of California. 3*41480Smckusick * All rights reserved. 4*41480Smckusick * 5*41480Smckusick * %sccs.include.redist.c% 6*41480Smckusick * 7*41480Smckusick * @(#)dmareg.h 7.1 (Berkeley) 05/08/90 8*41480Smckusick */ 9*41480Smckusick 10*41480Smckusick /* 11*41480Smckusick * Hardware layout for the 98620[ABC]: 12*41480Smckusick * 98620A (old 320s?): byte/word DMA in up to 64K chunks 13*41480Smckusick * 98620B (320s only): 98620A with programmable IPL 14*41480Smckusick * 98620C (all others): byte/word/longword DMA in up to 4Gb chunks 15*41480Smckusick */ 16*41480Smckusick #define v_char volatile char 17*41480Smckusick #define v_int volatile int 18*41480Smckusick #define vu_char volatile u_char 19*41480Smckusick #define vu_short volatile u_short 20*41480Smckusick #define vu_int volatile u_int 21*41480Smckusick 22*41480Smckusick struct dmaBdevice { 23*41480Smckusick v_char *dmaB_addr; 24*41480Smckusick vu_short dmaB_count; 25*41480Smckusick vu_short dmaB_cmd; 26*41480Smckusick #define dmaB_stat dmaB_cmd 27*41480Smckusick }; 28*41480Smckusick 29*41480Smckusick struct dmadevice { 30*41480Smckusick v_char *dma_addr; 31*41480Smckusick vu_int dma_count; 32*41480Smckusick vu_short dma_cmd; 33*41480Smckusick vu_short dma_stat; 34*41480Smckusick }; 35*41480Smckusick 36*41480Smckusick struct dmareg { 37*41480Smckusick struct dmaBdevice dma_Bchan0; 38*41480Smckusick struct dmaBdevice dma_Bchan1; 39*41480Smckusick /* the rest are 98620C specific */ 40*41480Smckusick v_char dma_id[4]; 41*41480Smckusick vu_char dma_cr; 42*41480Smckusick char dma_pad1[0xEB]; 43*41480Smckusick struct dmadevice dma_chan0; 44*41480Smckusick char dma_pad2[0xF4]; 45*41480Smckusick struct dmadevice dma_chan1; 46*41480Smckusick }; 47*41480Smckusick 48*41480Smckusick #define NDMA 2 49*41480Smckusick 50*41480Smckusick /* intr level must be >= level of any device using dma. i.e., splbio */ 51*41480Smckusick #define DMAINTLVL 5 52*41480Smckusick 53*41480Smckusick /* addresses */ 54*41480Smckusick #define DMA_BASE IOV(0x500000) 55*41480Smckusick 56*41480Smckusick /* command bits */ 57*41480Smckusick #define DMA_ENAB 0x0001 58*41480Smckusick #define DMA_WORD 0x0002 59*41480Smckusick #define DMA_WRT 0x0004 60*41480Smckusick #define DMA_PRI 0x0008 61*41480Smckusick #define DMA_IPL(x) (((x) - 3) << 4) 62*41480Smckusick #define DMA_LWORD 0x0100 63*41480Smckusick #define DMA_START 0x8000 64*41480Smckusick 65*41480Smckusick /* status bits */ 66*41480Smckusick #define DMA_ARMED 0x01 67*41480Smckusick #define DMA_INTR 0x02 68*41480Smckusick #define DMA_ACC 0x04 69*41480Smckusick #define DMA_HALT 0x08 70*41480Smckusick #define DMA_BERR 0x10 71*41480Smckusick #define DMA_ALIGN 0x20 72*41480Smckusick #define DMA_WRAP 0x40 73*41480Smckusick 74*41480Smckusick #ifdef KERNEL 75*41480Smckusick /* 76*41480Smckusick * Macros to attempt to hide the HW differences between the 98620B DMA 77*41480Smckusick * board and the 1TQ4-0401 DMA chip (68020C "board"). The latter 78*41480Smckusick * includes emulation registers for the former but you need to access 79*41480Smckusick * the "native-mode" registers directly in order to do 32-bit DMA. 80*41480Smckusick * 81*41480Smckusick * DMA_CLEAR: Clear interrupt on DMA board. We just use the 82*41480Smckusick * emulation registers on the 98620C as that is easiest. 83*41480Smckusick * DMA_STAT: Read status register. Again, we always read the 84*41480Smckusick * emulation register. Someday we might want to 85*41480Smckusick * look at the 98620C status to get the extended bits. 86*41480Smckusick * DMA_ARM: Load address, count and kick-off DMA. 87*41480Smckusick */ 88*41480Smckusick #define DMA_CLEAR(dc) { v_int dmaclr = (int)dc->sc_Bhwaddr->dmaB_addr; } 89*41480Smckusick #define DMA_STAT(dc) dc->sc_Bhwaddr->dmaB_stat 90*41480Smckusick 91*41480Smckusick #if defined(HP320) 92*41480Smckusick #define DMA_ARM(dc, ix) \ 93*41480Smckusick if (dc->sc_type == DMA_B) { \ 94*41480Smckusick register struct dmaBdevice *dma = dc->sc_Bhwaddr; \ 95*41480Smckusick dma->dmaB_addr = dc->sc_addr[ix]; \ 96*41480Smckusick dma->dmaB_count = dc->sc_count[ix] - 1; \ 97*41480Smckusick dma->dmaB_cmd = dc->sc_cmd; \ 98*41480Smckusick } else { \ 99*41480Smckusick register struct dmadevice *dma = dc->sc_hwaddr; \ 100*41480Smckusick dma->dma_addr = dc->sc_addr[ix]; \ 101*41480Smckusick dma->dma_count = dc->sc_count[ix] - 1; \ 102*41480Smckusick dma->dma_cmd = dc->sc_cmd; \ 103*41480Smckusick } 104*41480Smckusick #else 105*41480Smckusick #define DMA_ARM(dc, ix) \ 106*41480Smckusick { \ 107*41480Smckusick register struct dmadevice *dma = dc->sc_hwaddr; \ 108*41480Smckusick dma->dma_addr = dc->sc_addr[ix]; \ 109*41480Smckusick dma->dma_count = dc->sc_count[ix] - 1; \ 110*41480Smckusick dma->dma_cmd = dc->sc_cmd; \ 111*41480Smckusick } 112*41480Smckusick #endif 113*41480Smckusick #endif 114