xref: /csrg-svn/sys/hp300/dev/dmareg.h (revision 63151)
141480Smckusick /*
2*63151Sbostic  * Copyright (c) 1982, 1990, 1993
3*63151Sbostic  *	The Regents of the University of California.  All rights reserved.
441480Smckusick  *
541480Smckusick  * %sccs.include.redist.c%
641480Smckusick  *
7*63151Sbostic  *	@(#)dmareg.h	8.1 (Berkeley) 06/10/93
841480Smckusick  */
941480Smckusick 
1056507Sbostic #include <hp/dev/iotypes.h>		/* XXX */
1153930Shibler 
1241480Smckusick /*
1341480Smckusick  * Hardware layout for the 98620[ABC]:
1441480Smckusick  *	98620A (old 320s?):	byte/word DMA in up to 64K chunks
1541480Smckusick  *	98620B (320s only):	98620A with programmable IPL
1641480Smckusick  *	98620C (all others):	byte/word/longword DMA in up to 4Gb chunks
1741480Smckusick  */
1841480Smckusick 
1941480Smckusick struct	dmaBdevice {
2041480Smckusick 	v_char		*dmaB_addr;
2141480Smckusick 	vu_short	dmaB_count;
2241480Smckusick 	vu_short	dmaB_cmd;
2341480Smckusick #define	dmaB_stat	dmaB_cmd
2441480Smckusick };
2541480Smckusick 
2641480Smckusick struct	dmadevice {
2741480Smckusick 	v_char		*dma_addr;
2841480Smckusick 	vu_int		dma_count;
2941480Smckusick 	vu_short	dma_cmd;
3041480Smckusick 	vu_short	dma_stat;
3141480Smckusick };
3241480Smckusick 
3341480Smckusick struct	dmareg {
3441480Smckusick 	struct dmaBdevice dma_Bchan0;
3541480Smckusick 	struct dmaBdevice dma_Bchan1;
3641480Smckusick /* the rest are 98620C specific */
3741480Smckusick 	v_char		  dma_id[4];
3841480Smckusick 	vu_char		  dma_cr;
3941480Smckusick 	char		  dma_pad1[0xEB];
4041480Smckusick 	struct dmadevice  dma_chan0;
4141480Smckusick 	char		  dma_pad2[0xF4];
4241480Smckusick 	struct dmadevice  dma_chan1;
4341480Smckusick };
4441480Smckusick 
4541480Smckusick #define	NDMA		2
4641480Smckusick 
4741480Smckusick /* intr level must be >= level of any device using dma.  i.e., splbio */
4841480Smckusick #define	DMAINTLVL	5
4941480Smckusick 
5041480Smckusick /* addresses */
5149311Shibler #define	DMA_BASE	IIOV(0x500000)
5241480Smckusick 
5341480Smckusick /* command bits */
5441480Smckusick #define	DMA_ENAB	0x0001
5541480Smckusick #define	DMA_WORD	0x0002
5641480Smckusick #define	DMA_WRT		0x0004
5741480Smckusick #define	DMA_PRI		0x0008
5841480Smckusick #define	DMA_IPL(x)	(((x) - 3) << 4)
5941480Smckusick #define DMA_LWORD	0x0100
6041480Smckusick #define DMA_START	0x8000
6141480Smckusick 
6241480Smckusick /* status bits */
6341480Smckusick #define	DMA_ARMED	0x01
6441480Smckusick #define	DMA_INTR	0x02
6541480Smckusick #define DMA_ACC		0x04
6641480Smckusick #define DMA_HALT	0x08
6741480Smckusick #define DMA_BERR	0x10
6841480Smckusick #define DMA_ALIGN	0x20
6941480Smckusick #define DMA_WRAP	0x40
7041480Smckusick 
7141480Smckusick #ifdef KERNEL
7241480Smckusick /*
7341480Smckusick  * Macros to attempt to hide the HW differences between the 98620B DMA
7441480Smckusick  * board and the 1TQ4-0401 DMA chip (68020C "board").  The latter
7541480Smckusick  * includes emulation registers for the former but you need to access
7641480Smckusick  * the "native-mode" registers directly in order to do 32-bit DMA.
7741480Smckusick  *
7841480Smckusick  * DMA_CLEAR:	Clear interrupt on DMA board.  We just use the
7941480Smckusick  *		emulation registers on the 98620C as that is easiest.
8041480Smckusick  * DMA_STAT:	Read status register.  Again, we always read the
8141480Smckusick  *		emulation register.  Someday we might want to
8241480Smckusick  *		look at the 98620C status to get the extended bits.
8341480Smckusick  * DMA_ARM:	Load address, count and kick-off DMA.
8441480Smckusick  */
8541480Smckusick #define	DMA_CLEAR(dc)	{ v_int dmaclr = (int)dc->sc_Bhwaddr->dmaB_addr; }
8641480Smckusick #define	DMA_STAT(dc)	dc->sc_Bhwaddr->dmaB_stat
8741480Smckusick 
8841480Smckusick #if defined(HP320)
8945483Smckusick #define	DMA_ARM(dc)	\
9041480Smckusick 	if (dc->sc_type == DMA_B) { \
9141480Smckusick 		register struct dmaBdevice *dma = dc->sc_Bhwaddr; \
9245483Smckusick 		dma->dmaB_addr = dc->sc_cur->dc_addr; \
9345483Smckusick 		dma->dmaB_count = dc->sc_cur->dc_count - 1; \
9441480Smckusick 		dma->dmaB_cmd = dc->sc_cmd; \
9541480Smckusick 	} else { \
9641480Smckusick 		register struct dmadevice *dma = dc->sc_hwaddr; \
9745483Smckusick 		dma->dma_addr = dc->sc_cur->dc_addr; \
9845483Smckusick 		dma->dma_count = dc->sc_cur->dc_count - 1; \
9941480Smckusick 		dma->dma_cmd = dc->sc_cmd; \
10041480Smckusick 	}
10141480Smckusick #else
10245483Smckusick #define	DMA_ARM(dc)	\
10341480Smckusick 	{ \
10441480Smckusick 		register struct dmadevice *dma = dc->sc_hwaddr; \
10545483Smckusick 		dma->dma_addr = dc->sc_cur->dc_addr; \
10645483Smckusick 		dma->dma_count = dc->sc_cur->dc_count - 1; \
10741480Smckusick 		dma->dma_cmd = dc->sc_cmd; \
10841480Smckusick 	}
10941480Smckusick #endif
11041480Smckusick #endif
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