141480Smckusick /* 241480Smckusick * Copyright (c) 1988 University of Utah. 341480Smckusick * Copyright (c) 1982, 1986, 1990 The Regents of the University of California. 441480Smckusick * All rights reserved. 541480Smckusick * 641480Smckusick * This code is derived from software contributed to Berkeley by 741480Smckusick * the Systems Programming Group of the University of Utah Computer 841480Smckusick * Science Department. 941480Smckusick * 1041480Smckusick * %sccs.include.redist.c% 1141480Smckusick * 12*53930Shibler * from: Utah $Hdr: dcmreg.h 1.7 92/01/21$ 1341480Smckusick * 14*53930Shibler * @(#)dcmreg.h 7.5 (Berkeley) 06/05/92 1541480Smckusick */ 1641480Smckusick 17*53930Shibler #ifdef KERNEL 18*53930Shibler #include "hp/dev/iotypes.h" /* XXX */ 19*53930Shibler #else 20*53930Shibler #include <hp/dev/iotypes.h> /* XXX */ 21*53930Shibler #endif 22*53930Shibler 2341480Smckusick struct dcmdevice { /* host address, only odd bytes addressed */ 2441480Smckusick u_char dcm_pad0; 25*53930Shibler vu_char dcm_rsid; /* Reset / ID 0001 */ 2641480Smckusick u_char dcm_pad1; 27*53930Shibler vu_char dcm_ic; /* Interrupt control register 0003 */ 2841480Smckusick u_char dcm_pad2; 29*53930Shibler vu_char dcm_sem; /* Semaphore register 0005 */ 3042355Smckusick u_char dcm_pad3[0x7ffa]; /* Unaddressable 0006-7fff */ 3141480Smckusick u_char dcm_pad4; 32*53930Shibler vu_char dcm_iir; /* Interrupt ident register 8001 */ 3341480Smckusick u_char dcm_pad5; 34*53930Shibler vu_char dcm_cr; /* Command register 8003 */ 3542355Smckusick u_char dcm_pad6[0x3fc]; /* Card scratch 8004-83ff */ 3642355Smckusick struct dcmrfifo { 3742355Smckusick u_char ptr_pad1; 38*53930Shibler vu_char data_char; 3942355Smckusick u_char ptr_pad2; 40*53930Shibler vu_char data_stat; 4142355Smckusick } dcm_rfifos[4][0x80]; /* Receive queues 8400 */ 4241480Smckusick struct { 4342355Smckusick u_char ptr_pad1; 44*53930Shibler vu_char data_data; 4542355Smckusick } dcm_bmap[0x100]; /* Bitmap table 8c00 */ 4641480Smckusick struct { 4742355Smckusick u_char ptr_pad; 48*53930Shibler vu_char ptr; 4942355Smckusick } dcm_rhead[4]; /* Fifo head - receive 8e00 */ 5041480Smckusick struct { 5142355Smckusick u_char ptr_pad; 52*53930Shibler vu_char ptr; 5342355Smckusick } dcm_rtail[4]; /* Fifo tail - receive 8e08 */ 5441480Smckusick struct { 5542355Smckusick u_char ptr_pad; 56*53930Shibler vu_char ptr; 5742355Smckusick } dcm_thead[4]; /* Fifo head - transmit 8e10 */ 5841480Smckusick struct { 5942355Smckusick u_char ptr_pad; 60*53930Shibler vu_char ptr; 6142355Smckusick } dcm_ttail[4]; /* Fifo tail - transmit 8e18 */ 6241480Smckusick struct { 6342355Smckusick u_char pad1; 64*53930Shibler vu_char dcm_conf; 6542355Smckusick u_char pad2; 66*53930Shibler vu_char dcm_baud; 6742355Smckusick } dcm_data[4]; /* Configuration registers 8e20 */ 6845482Smckusick struct modemreg { 6945482Smckusick u_char pad0; 70*53930Shibler vu_char mdmin; /* Modem in 8e31 */ 7145482Smckusick u_char pad1; 72*53930Shibler vu_char mdmout; /* Modem out 8e33 */ 7345482Smckusick u_char pad2; 74*53930Shibler vu_char mdmmsk; /* Modem mask 8e35 */ 7545482Smckusick } dcm_modem0; 7641480Smckusick struct { 7741480Smckusick u_char pad1; 78*53930Shibler vu_char dcm_data; 7942355Smckusick } dcm_cmdtab[4]; /* Command tables 8e36 */ 8041480Smckusick struct { 8141480Smckusick u_char pad1; 82*53930Shibler vu_char dcm_data; 8342355Smckusick } dcm_icrtab[4]; /* Interrupt data 8e3e */ 8441480Smckusick u_char dcm_pad10; 85*53930Shibler vu_char dcm_stcon; /* Self test condition 8e47 */ 8645482Smckusick struct modemreg dcm_modem1; /* 638 Modem port1 8e48 */ 8745482Smckusick struct modemreg dcm_modem2; /* 638 Modem port2 8e4e */ 8845482Smckusick struct modemreg dcm_modem3; /* 638 Modem port3 8e54 */ 8945482Smckusick u_char dcm_pad11; 90*53930Shibler vu_char dcm_modemchng; /* 638 Modem change mask 8e5b */ 9145482Smckusick u_char dcm_pad12; 92*53930Shibler vu_char dcm_modemintr; /* 638 Modem interrupt mask 8e5d */ 9345482Smckusick u_char dcm_pad13[0x82]; /* Undef Shared Ram 8e5e-8edf */ 9442355Smckusick struct dcmtfifo { 9541480Smckusick u_char ptr_pad1; 96*53930Shibler vu_char data_char; 9742355Smckusick } dcm_tfifos[4][0x10]; /* Transmit queues 8ee0 */ 9841480Smckusick }; 9941480Smckusick 10042355Smckusick /* 10142355Smckusick * Overlay structure for port specific queue "registers". 10242355Smckusick * Starts at offset 0x8E00+(port*2). 10342355Smckusick */ 10442355Smckusick struct dcmpreg { 10542355Smckusick u_char pad0; /* +00 */ 106*53930Shibler vu_char r_head; /* +01 */ 10742355Smckusick u_char pad1[7]; /* +02 */ 108*53930Shibler vu_char r_tail; /* +09 */ 10942355Smckusick u_char pad2[7]; /* +0A */ 110*53930Shibler vu_char t_head; /* +11 */ 11142355Smckusick u_char pad3[7]; /* +12 */ 112*53930Shibler vu_char t_tail; /* +19 */ 11342355Smckusick }; 11442355Smckusick #define dcm_preg(d, p) ((struct dcmpreg *)((u_int)(d)+0x8e00+(p)*2)) 11542355Smckusick 11641480Smckusick /* interface reset/id */ 11741480Smckusick #define DCMCON 0x80 /* REMOTE/LOCAL switch, read */ 11841480Smckusick #define DCMID 0x5 /* hardwired card id, read */ 11941480Smckusick #define DCMRS 0x80 /* software reset, write */ 12041480Smckusick 12141480Smckusick /* interrupt control */ 12241480Smckusick #define DCMIPL(x) ((((x) >> 4) & 3) + 3) /* interupt level, read */ 12341480Smckusick #define IC_IR 0x40 /* interupt request, read */ 12441480Smckusick #define IC_IE 0x80 /* interupt enable, write */ 12541480Smckusick #define IC_ID 0x00 /* interupt disable, write */ 12641480Smckusick 12741480Smckusick 12841480Smckusick /* Semaphore control */ 12941480Smckusick #define SEM_BSY 0x80 /* read */ 13041480Smckusick #define SEM_CLR 0xFF /* write */ 13141480Smckusick #define SEM_LOCK(dcm) while ((dcm)->dcm_sem & SEM_BSY) 13241480Smckusick #define SEM_UNLOCK(dcm) (dcm)->dcm_sem = SEM_CLR 13341480Smckusick 13441480Smckusick /* command register */ 13541480Smckusick #define CR_PORT0 0x1 13641480Smckusick #define CR_PORT1 0x2 13741480Smckusick #define CR_PORT2 0x4 13841480Smckusick #define CR_PORT3 0x8 13941480Smckusick #define CR_MODM 0x10 /* change modem output lines */ 14041480Smckusick #define CR_TIMER 0x20 /* 16ms interrupt timer toggle */ 14141480Smckusick #define CR_SELFT 0x40 /* run self test */ 14241480Smckusick #define CR_MASK 0x7f 14341480Smckusick 14441480Smckusick /* interrupt ident register */ 14541480Smckusick #define IIR_PORT0 0x1 14641480Smckusick #define IIR_PORT1 0x2 14741480Smckusick #define IIR_PORT2 0x4 14841480Smckusick #define IIR_PORT3 0x8 14941480Smckusick #define IIR_SELFT 0x10 /* self test completed */ 15041480Smckusick #define IIR_MODM 0x20 /* change in modem input lines */ 15141480Smckusick #define IIR_TIMEO 0x40 /* Time out */ 15241480Smckusick #define IIR_MASK 0x7f 15341480Smckusick 15441480Smckusick /* self test cond reg */ 15541480Smckusick #define ST_OK 0xe0 15641480Smckusick 15741480Smckusick /* Line configuration register */ 15841480Smckusick #define LC_PNO 0x00 15941480Smckusick #define LC_PODD 0x01 16041480Smckusick #define LC_PEVEN 0x02 16141480Smckusick #define LC_PMSK 0x03 16241480Smckusick 16341480Smckusick #define LC_1STOP 0x00 16441480Smckusick #define LC_1HSTOP 0x04 16541480Smckusick #define LC_2STOP 0x08 16641480Smckusick #define LC_STOPMSK 0x0b 16741480Smckusick 16841480Smckusick #define LC_8BITS 0x30 16941480Smckusick #define LC_7BITS 0x20 17041480Smckusick #define LC_6BITS 0x10 17141480Smckusick #define LC_5BITS 0x00 17241480Smckusick #define LC_BITMSK 0x30 17341480Smckusick 17441480Smckusick /* baud reg */ 17541480Smckusick #define BR_0 0x00 17641480Smckusick #define BR_50 0x01 17741480Smckusick #define BR_75 0x02 17841480Smckusick #define BR_110 0x03 17941480Smckusick #define BR_134 0x04 18041480Smckusick #define BR_150 0x05 18141480Smckusick #define BR_300 0x06 18241480Smckusick #define BR_600 0x07 18341480Smckusick #define BR_900 0x08 18441480Smckusick #define BR_1200 0x09 18541480Smckusick #define BR_1800 0x0a 18641480Smckusick #define BR_2400 0x0b 18741480Smckusick #define BR_3600 0x0c 18841480Smckusick #define BR_4800 0x0d 18941480Smckusick #define BR_7200 0x0e 19041480Smckusick #define BR_9600 0x0f 19141480Smckusick #define BR_19200 0x10 19241480Smckusick #define BR_38400 0x11 19341480Smckusick 19441480Smckusick /* modem input register */ 19541480Smckusick #define MI_CTS 0x08 19641480Smckusick #define MI_DM 0x04 19741480Smckusick #define MI_CD 0x02 19841480Smckusick #define MI_RI 0x01 19941480Smckusick 20041480Smckusick /* modem output register */ 20141480Smckusick #define MO_SR 0x04 20241480Smckusick #define MO_DTR 0x02 20341480Smckusick #define MO_RTS 0x01 20441480Smckusick #define MO_ON ((MO_DTR) | (MO_RTS)) 20541480Smckusick #define MO_OFF 0x00 20641480Smckusick 20741480Smckusick /* cmd-tab values, write */ 20841480Smckusick #define CT_CON 0x1 /* configuration change */ 20941480Smckusick #define CT_TX 0x2 /* transmit buffer not empty */ 21041480Smckusick #define CT_BRK 0x4 /* toggle BREAK */ 21141480Smckusick 21241480Smckusick /* icr-tab values, read */ 21341480Smckusick #define IT_TX 0x1 /* transmit buffer empty */ 21441480Smckusick #define IT_SPEC 0x2 /* special character received */ 21541480Smckusick 21641480Smckusick /* data errors */ 21741480Smckusick #define RD_OVF 0x08 21841480Smckusick #define RD_BD 0x10 21941480Smckusick #define RD_PE 0x20 22041480Smckusick #define RD_OE 0x40 22141480Smckusick #define RD_FE 0x80 22241480Smckusick #define RD_MASK 0xf8 22341480Smckusick 22441480Smckusick /* Transmit/Receive masks */ 22541480Smckusick #define TX_MASK 0x0f 22641480Smckusick #define RX_MASK 0xff 22741480Smckusick 22841480Smckusick /* 22943418Shibler * WARNING: Serial console is assumed to be the lowest select-code card 23043418Shibler * and that card must be logical unit 0 in the kernel. Also, CONUNIT must 23143418Shibler * be 1, the port affected by the REMOTE/LOCAL switch. 23241480Smckusick */ 23341480Smckusick #define CONUNIT (1) 234