1*41480Smckusick /* 2*41480Smckusick * Copyright (c) 1988 University of Utah. 3*41480Smckusick * Copyright (c) 1982, 1986, 1990 The Regents of the University of California. 4*41480Smckusick * All rights reserved. 5*41480Smckusick * 6*41480Smckusick * This code is derived from software contributed to Berkeley by 7*41480Smckusick * the Systems Programming Group of the University of Utah Computer 8*41480Smckusick * Science Department. 9*41480Smckusick * 10*41480Smckusick * %sccs.include.redist.c% 11*41480Smckusick * 12*41480Smckusick * from: Utah $Hdr: dcmreg.h 1.3 89/08/23$ 13*41480Smckusick * 14*41480Smckusick * @(#)dcmreg.h 7.1 (Berkeley) 05/08/90 15*41480Smckusick */ 16*41480Smckusick 17*41480Smckusick struct dcmdevice { /* host address, only odd bytes addressed */ 18*41480Smckusick u_char dcm_pad0; 19*41480Smckusick volatile u_char dcm_rsid; /* Reset / ID 0001 */ 20*41480Smckusick u_char dcm_pad1; 21*41480Smckusick volatile u_char dcm_ic; /* Interrupt control register 0003 */ 22*41480Smckusick u_char dcm_pad2; 23*41480Smckusick volatile u_char dcm_sem; /* Semaphore register 0005 */ 24*41480Smckusick u_char dcm_pad3[0x7ffa]; /* Unaddressable 0006-7fff */ 25*41480Smckusick u_char dcm_pad4; 26*41480Smckusick volatile u_char dcm_iir; /* Interrupt ident register 8001 */ 27*41480Smckusick u_char dcm_pad5; 28*41480Smckusick volatile u_char dcm_cr; /* Command register 8003 */ 29*41480Smckusick u_char dcm_pad6[0x3fc]; /* Card scratch 8004-83ff */ 30*41480Smckusick struct { 31*41480Smckusick u_char ptr_pad1; 32*41480Smckusick volatile u_char data_char; 33*41480Smckusick u_char ptr_pad2; 34*41480Smckusick volatile u_char data_stat; 35*41480Smckusick } dcm_rfifos[4][0x80]; /* Receive queues 8400 */ 36*41480Smckusick struct { 37*41480Smckusick u_char ptr_pad1; 38*41480Smckusick volatile u_char data_data; 39*41480Smckusick } dcm_bmap[0x100]; /* Bitmap table 8c00 */ 40*41480Smckusick struct { 41*41480Smckusick u_char ptr_pad; 42*41480Smckusick volatile u_char ptr; 43*41480Smckusick } dcm_rhead[4]; /* Fifo head - receive 8e00 */ 44*41480Smckusick struct { 45*41480Smckusick u_char ptr_pad; 46*41480Smckusick volatile u_char ptr; 47*41480Smckusick } dcm_rtail[4]; /* Fifo tail - receive 8e08 */ 48*41480Smckusick struct { 49*41480Smckusick u_char ptr_pad; 50*41480Smckusick volatile u_char ptr; 51*41480Smckusick } dcm_thead[4]; /* Fifo head - transmit 8e10 */ 52*41480Smckusick struct { 53*41480Smckusick u_char ptr_pad; 54*41480Smckusick volatile u_char ptr; 55*41480Smckusick } dcm_ttail[4]; /* Fifo tail - transmit 8e18 */ 56*41480Smckusick struct { 57*41480Smckusick u_char pad1; 58*41480Smckusick volatile u_char dcm_conf; 59*41480Smckusick u_char pad2; 60*41480Smckusick volatile u_char dcm_baud; 61*41480Smckusick } dcm_data[4]; /* Configuration registers 8e20 */ 62*41480Smckusick u_char dcm_pad7; 63*41480Smckusick volatile u_char dcm_mdmin; /* Modem in 8e31 */ 64*41480Smckusick u_char dcm_pad8; 65*41480Smckusick volatile u_char dcm_mdmout; /* Modem out 8e33 */ 66*41480Smckusick u_char dcm_pad9; 67*41480Smckusick volatile u_char dcm_mdmmsk; /* Modem mask 8e35 */ 68*41480Smckusick struct { 69*41480Smckusick u_char pad1; 70*41480Smckusick volatile u_char dcm_data; 71*41480Smckusick } dcm_cmdtab[4]; /* Command tables 8e36 */ 72*41480Smckusick struct { 73*41480Smckusick u_char pad1; 74*41480Smckusick volatile u_char dcm_data; 75*41480Smckusick } dcm_icrtab[4]; /* Interrupt data 8e3e */ 76*41480Smckusick u_char dcm_pad10; 77*41480Smckusick volatile u_char dcm_stcon; /* Self test condition 8e47 */ 78*41480Smckusick u_char dcm_pad11[0x98]; /* Undef SR regs 8e48-8edf */ 79*41480Smckusick struct { 80*41480Smckusick u_char ptr_pad1; 81*41480Smckusick volatile u_char data_char; 82*41480Smckusick } dcm_tfifos[4][0x10]; /* Transmit queues 8ee0 */ 83*41480Smckusick }; 84*41480Smckusick 85*41480Smckusick /* interface reset/id */ 86*41480Smckusick #define DCMCON 0x80 /* REMOTE/LOCAL switch, read */ 87*41480Smckusick #define DCMID 0x5 /* hardwired card id, read */ 88*41480Smckusick #define DCMRS 0x80 /* software reset, write */ 89*41480Smckusick 90*41480Smckusick /* interrupt control */ 91*41480Smckusick #define DCMIPL(x) ((((x) >> 4) & 3) + 3) /* interupt level, read */ 92*41480Smckusick #define IC_IR 0x40 /* interupt request, read */ 93*41480Smckusick #define IC_IE 0x80 /* interupt enable, write */ 94*41480Smckusick #define IC_ID 0x00 /* interupt disable, write */ 95*41480Smckusick 96*41480Smckusick 97*41480Smckusick /* Semaphore control */ 98*41480Smckusick #define SEM_BSY 0x80 /* read */ 99*41480Smckusick #define SEM_CLR 0xFF /* write */ 100*41480Smckusick #define SEM_LOCK(dcm) while ((dcm)->dcm_sem & SEM_BSY) 101*41480Smckusick #define SEM_UNLOCK(dcm) (dcm)->dcm_sem = SEM_CLR 102*41480Smckusick 103*41480Smckusick /* command register */ 104*41480Smckusick #define CR_PORT0 0x1 105*41480Smckusick #define CR_PORT1 0x2 106*41480Smckusick #define CR_PORT2 0x4 107*41480Smckusick #define CR_PORT3 0x8 108*41480Smckusick #define CR_MODM 0x10 /* change modem output lines */ 109*41480Smckusick #define CR_TIMER 0x20 /* 16ms interrupt timer toggle */ 110*41480Smckusick #define CR_SELFT 0x40 /* run self test */ 111*41480Smckusick #define CR_MASK 0x7f 112*41480Smckusick 113*41480Smckusick /* interrupt ident register */ 114*41480Smckusick #define IIR_PORT0 0x1 115*41480Smckusick #define IIR_PORT1 0x2 116*41480Smckusick #define IIR_PORT2 0x4 117*41480Smckusick #define IIR_PORT3 0x8 118*41480Smckusick #define IIR_SELFT 0x10 /* self test completed */ 119*41480Smckusick #define IIR_MODM 0x20 /* change in modem input lines */ 120*41480Smckusick #define IIR_TIMEO 0x40 /* Time out */ 121*41480Smckusick #define IIR_MASK 0x7f 122*41480Smckusick 123*41480Smckusick /* self test cond reg */ 124*41480Smckusick #define ST_OK 0xe0 125*41480Smckusick 126*41480Smckusick /* Line configuration register */ 127*41480Smckusick #define LC_PNO 0x00 128*41480Smckusick #define LC_PODD 0x01 129*41480Smckusick #define LC_PEVEN 0x02 130*41480Smckusick #define LC_PMSK 0x03 131*41480Smckusick 132*41480Smckusick #define LC_1STOP 0x00 133*41480Smckusick #define LC_1HSTOP 0x04 134*41480Smckusick #define LC_2STOP 0x08 135*41480Smckusick #define LC_STOPMSK 0x0b 136*41480Smckusick 137*41480Smckusick #define LC_8BITS 0x30 138*41480Smckusick #define LC_7BITS 0x20 139*41480Smckusick #define LC_6BITS 0x10 140*41480Smckusick #define LC_5BITS 0x00 141*41480Smckusick #define LC_BITMSK 0x30 142*41480Smckusick 143*41480Smckusick /* baud reg */ 144*41480Smckusick #define BR_0 0x00 145*41480Smckusick #define BR_50 0x01 146*41480Smckusick #define BR_75 0x02 147*41480Smckusick #define BR_110 0x03 148*41480Smckusick #define BR_134 0x04 149*41480Smckusick #define BR_150 0x05 150*41480Smckusick #define BR_300 0x06 151*41480Smckusick #define BR_600 0x07 152*41480Smckusick #define BR_900 0x08 153*41480Smckusick #define BR_1200 0x09 154*41480Smckusick #define BR_1800 0x0a 155*41480Smckusick #define BR_2400 0x0b 156*41480Smckusick #define BR_3600 0x0c 157*41480Smckusick #define BR_4800 0x0d 158*41480Smckusick #define BR_7200 0x0e 159*41480Smckusick #define BR_9600 0x0f 160*41480Smckusick #define BR_19200 0x10 161*41480Smckusick #define BR_38400 0x11 162*41480Smckusick 163*41480Smckusick /* modem input register */ 164*41480Smckusick #define MI_CTS 0x08 165*41480Smckusick #define MI_DM 0x04 166*41480Smckusick #define MI_CD 0x02 167*41480Smckusick #define MI_RI 0x01 168*41480Smckusick 169*41480Smckusick /* modem output register */ 170*41480Smckusick #define MO_SR 0x04 171*41480Smckusick #define MO_DTR 0x02 172*41480Smckusick #define MO_RTS 0x01 173*41480Smckusick #define MO_ON ((MO_DTR) | (MO_RTS)) 174*41480Smckusick #define MO_OFF 0x00 175*41480Smckusick 176*41480Smckusick /* cmd-tab values, write */ 177*41480Smckusick #define CT_CON 0x1 /* configuration change */ 178*41480Smckusick #define CT_TX 0x2 /* transmit buffer not empty */ 179*41480Smckusick #define CT_BRK 0x4 /* toggle BREAK */ 180*41480Smckusick 181*41480Smckusick /* icr-tab values, read */ 182*41480Smckusick #define IT_TX 0x1 /* transmit buffer empty */ 183*41480Smckusick #define IT_SPEC 0x2 /* special character received */ 184*41480Smckusick 185*41480Smckusick /* data errors */ 186*41480Smckusick #define RD_OVF 0x08 187*41480Smckusick #define RD_BD 0x10 188*41480Smckusick #define RD_PE 0x20 189*41480Smckusick #define RD_OE 0x40 190*41480Smckusick #define RD_FE 0x80 191*41480Smckusick #define RD_MASK 0xf8 192*41480Smckusick 193*41480Smckusick /* Transmit/Receive masks */ 194*41480Smckusick #define TX_MASK 0x0f 195*41480Smckusick #define RX_MASK 0xff 196*41480Smckusick 197*41480Smckusick /* 198*41480Smckusick * WARNING: Serial console is assumed to be at SC13 199*41480Smckusick * and CONUNIT must be 1, signeled by REMOTE/LOCAL switch on card 200*41480Smckusick */ 201*41480Smckusick #define CONADDR ((struct dcmdevice *)(IOV(EXTIOBASE + (13 * IOCARDSIZE)))) 202*41480Smckusick #define CONUNIT (1) 203