xref: /csrg-svn/sys/hp300/dev/dcmreg.h (revision 63151)
141480Smckusick /*
241480Smckusick  * Copyright (c) 1988 University of Utah.
3*63151Sbostic  * Copyright (c) 1982, 1986, 1990, 1993
4*63151Sbostic  *	The Regents of the University of California.  All rights reserved.
541480Smckusick  *
641480Smckusick  * This code is derived from software contributed to Berkeley by
741480Smckusick  * the Systems Programming Group of the University of Utah Computer
841480Smckusick  * Science Department.
941480Smckusick  *
1041480Smckusick  * %sccs.include.redist.c%
1141480Smckusick  *
1253930Shibler  * from: Utah $Hdr: dcmreg.h 1.7 92/01/21$
1341480Smckusick  *
14*63151Sbostic  *	@(#)dcmreg.h	8.1 (Berkeley) 06/10/93
1541480Smckusick  */
1641480Smckusick 
1756507Sbostic #include <hp/dev/iotypes.h>		/* XXX */
1853930Shibler 
1941480Smckusick struct dcmdevice {	   /* host address, only odd bytes addressed */
2041480Smckusick 	u_char	dcm_pad0;
2153930Shibler 	vu_char	dcm_rsid;		/* Reset / ID			0001 */
2241480Smckusick 	u_char	dcm_pad1;
2353930Shibler 	vu_char	dcm_ic;			/* Interrupt control register	0003 */
2441480Smckusick 	u_char	dcm_pad2;
2553930Shibler 	vu_char	dcm_sem;		/* Semaphore register		0005 */
2642355Smckusick 	u_char  dcm_pad3[0x7ffa];	/* Unaddressable	0006-7fff */
2741480Smckusick 	u_char	dcm_pad4;
2853930Shibler 	vu_char	dcm_iir;		/* Interrupt ident register	8001 */
2941480Smckusick 	u_char	dcm_pad5;
3053930Shibler 	vu_char	dcm_cr;			/* Command register		8003 */
3142355Smckusick 	u_char  dcm_pad6[0x3fc];	/* Card scratch		8004-83ff */
3242355Smckusick 	struct	dcmrfifo {
3342355Smckusick 		u_char	ptr_pad1;
3453930Shibler 		vu_char	data_char;
3542355Smckusick 		u_char	ptr_pad2;
3653930Shibler 		vu_char	data_stat;
3742355Smckusick 	} dcm_rfifos[4][0x80];		/* Receive queues		8400 */
3841480Smckusick 	struct  {
3942355Smckusick 		u_char	ptr_pad1;
4053930Shibler 		vu_char	data_data;
4142355Smckusick 	} dcm_bmap[0x100];		/* Bitmap table			8c00 */
4241480Smckusick 	struct  {
4342355Smckusick 		u_char	ptr_pad;
4453930Shibler 		vu_char	ptr;
4542355Smckusick 	} dcm_rhead[4];			/* Fifo head - receive		8e00 */
4641480Smckusick 	struct  {
4742355Smckusick 		u_char  ptr_pad;
4853930Shibler 		vu_char  ptr;
4942355Smckusick 	} dcm_rtail[4];			/* Fifo tail - receive		8e08 */
5041480Smckusick 	struct  {
5142355Smckusick 		u_char	ptr_pad;
5253930Shibler 		vu_char	ptr;
5342355Smckusick 	} dcm_thead[4];			/* Fifo head - transmit		8e10 */
5441480Smckusick 	struct  {
5542355Smckusick 		u_char	ptr_pad;
5653930Shibler 		vu_char	ptr;
5742355Smckusick 	} dcm_ttail[4];			/* Fifo tail - transmit		8e18 */
5841480Smckusick 	struct  {
5942355Smckusick 		u_char	pad1;
6053930Shibler 		vu_char	dcm_conf;
6142355Smckusick 		u_char	pad2;
6253930Shibler 		vu_char	dcm_baud;
6342355Smckusick 	} dcm_data[4];			/* Configuration registers	8e20 */
6445482Smckusick 	struct	modemreg {
6545482Smckusick 		u_char	pad0;
6653930Shibler 		vu_char mdmin;		/* Modem in			8e31 */
6745482Smckusick 		u_char  pad1;
6853930Shibler 		vu_char mdmout;		/* Modem out			8e33 */
6945482Smckusick 		u_char  pad2;
7053930Shibler 		vu_char mdmmsk;		/* Modem mask			8e35 */
7145482Smckusick 	} dcm_modem0;
7241480Smckusick 	struct  {
7341480Smckusick 		u_char pad1;
7453930Shibler 		vu_char dcm_data;
7542355Smckusick 	} dcm_cmdtab[4];		/* Command tables		8e36 */
7641480Smckusick 	struct  {
7741480Smckusick 		u_char pad1;
7853930Shibler 		vu_char dcm_data;
7942355Smckusick 	} dcm_icrtab[4];		/* Interrupt data		8e3e */
8041480Smckusick 	u_char  dcm_pad10;
8153930Shibler 	vu_char dcm_stcon;		/* Self test condition		8e47 */
8245482Smckusick 	struct modemreg dcm_modem1;	/* 638 Modem port1		8e48 */
8345482Smckusick 	struct modemreg dcm_modem2;	/* 638 Modem port2		8e4e */
8445482Smckusick 	struct modemreg dcm_modem3;	/* 638 Modem port3		8e54 */
8545482Smckusick 	u_char	dcm_pad11;
8653930Shibler 	vu_char	dcm_modemchng;		/* 638 Modem change mask	8e5b */
8745482Smckusick 	u_char	dcm_pad12;
8853930Shibler 	vu_char	dcm_modemintr;		/* 638 Modem interrupt mask	8e5d */
8945482Smckusick 	u_char  dcm_pad13[0x82];	/* Undef Shared Ram	8e5e-8edf */
9042355Smckusick 	struct	dcmtfifo {
9141480Smckusick 	    u_char  ptr_pad1;
9253930Shibler 	    vu_char  data_char;
9342355Smckusick 	} dcm_tfifos[4][0x10];		/* Transmit queues		8ee0 */
9441480Smckusick };
9541480Smckusick 
9642355Smckusick /*
9742355Smckusick  * Overlay structure for port specific queue "registers".
9842355Smckusick  * Starts at offset 0x8E00+(port*2).
9942355Smckusick  */
10042355Smckusick struct	dcmpreg {
10142355Smckusick 	u_char		pad0;		/* +00 */
10253930Shibler 	vu_char	r_head;			/* +01 */
10342355Smckusick 	u_char		pad1[7];	/* +02 */
10453930Shibler 	vu_char	r_tail;			/* +09 */
10542355Smckusick 	u_char		pad2[7];	/* +0A */
10653930Shibler 	vu_char	t_head;			/* +11 */
10742355Smckusick 	u_char		pad3[7];	/* +12 */
10853930Shibler 	vu_char	t_tail;			/* +19 */
10942355Smckusick };
11042355Smckusick #define	dcm_preg(d, p)	((struct dcmpreg *)((u_int)(d)+0x8e00+(p)*2))
11142355Smckusick 
11241480Smckusick /* interface reset/id */
11341480Smckusick #define DCMCON          0x80	/* REMOTE/LOCAL switch, read */
11441480Smckusick #define	DCMID		0x5	/* hardwired card id, read */
11541480Smckusick #define	DCMRS		0x80	/* software reset, write */
11641480Smckusick 
11741480Smckusick /* interrupt control */
11841480Smckusick #define	DCMIPL(x)	((((x) >> 4) & 3) + 3)	/* interupt level, read */
11941480Smckusick #define	IC_IR		0x40	/* interupt request, read */
12041480Smckusick #define	IC_IE		0x80	/* interupt enable, write */
12141480Smckusick #define	IC_ID		0x00	/* interupt disable, write */
12241480Smckusick 
12341480Smckusick 
12441480Smckusick /* Semaphore control */
12541480Smckusick #define	SEM_BSY		0x80	/* read */
12641480Smckusick #define SEM_CLR         0xFF	/* write */
12741480Smckusick #define SEM_LOCK(dcm)	while ((dcm)->dcm_sem & SEM_BSY)
12841480Smckusick #define SEM_UNLOCK(dcm)	(dcm)->dcm_sem = SEM_CLR
12941480Smckusick 
13041480Smckusick /* command register */
13141480Smckusick #define	CR_PORT0	0x1
13241480Smckusick #define	CR_PORT1	0x2
13341480Smckusick #define	CR_PORT2	0x4
13441480Smckusick #define	CR_PORT3	0x8
13541480Smckusick #define	CR_MODM		0x10	/* change modem output lines */
13641480Smckusick #define	CR_TIMER	0x20	/* 16ms interrupt timer toggle */
13741480Smckusick #define	CR_SELFT	0x40	/* run self test */
13841480Smckusick #define CR_MASK		0x7f
13941480Smckusick 
14041480Smckusick /* interrupt ident register */
14141480Smckusick #define	IIR_PORT0	0x1
14241480Smckusick #define	IIR_PORT1	0x2
14341480Smckusick #define	IIR_PORT2	0x4
14441480Smckusick #define	IIR_PORT3	0x8
14541480Smckusick #define	IIR_SELFT	0x10	/* self test completed */
14641480Smckusick #define	IIR_MODM	0x20	/* change in modem input lines */
14741480Smckusick #define	IIR_TIMEO	0x40	/* Time out */
14841480Smckusick #define IIR_MASK	0x7f
14941480Smckusick 
15041480Smckusick /* self test cond reg */
15141480Smckusick #define ST_OK           0xe0
15241480Smckusick 
15341480Smckusick /* Line configuration register */
15441480Smckusick #define	LC_PNO		0x00
15541480Smckusick #define	LC_PODD		0x01
15641480Smckusick #define	LC_PEVEN	0x02
15741480Smckusick #define	LC_PMSK		0x03
15841480Smckusick 
15941480Smckusick #define	LC_1STOP	0x00
16041480Smckusick #define	LC_1HSTOP	0x04
16141480Smckusick #define	LC_2STOP	0x08
16241480Smckusick #define	LC_STOPMSK	0x0b
16341480Smckusick 
16441480Smckusick #define	LC_8BITS	0x30
16541480Smckusick #define	LC_7BITS	0x20
16641480Smckusick #define	LC_6BITS	0x10
16741480Smckusick #define	LC_5BITS	0x00
16841480Smckusick #define	LC_BITMSK	0x30
16941480Smckusick 
17041480Smckusick /* baud reg */
17141480Smckusick #define BR_0		0x00
17241480Smckusick #define BR_50		0x01
17341480Smckusick #define BR_75		0x02
17441480Smckusick #define BR_110		0x03
17541480Smckusick #define BR_134  	0x04
17641480Smckusick #define BR_150		0x05
17741480Smckusick #define BR_300		0x06
17841480Smckusick #define BR_600		0x07
17941480Smckusick #define BR_900		0x08
18041480Smckusick #define BR_1200		0x09
18141480Smckusick #define BR_1800		0x0a
18241480Smckusick #define BR_2400		0x0b
18341480Smckusick #define BR_3600		0x0c
18441480Smckusick #define BR_4800		0x0d
18541480Smckusick #define BR_7200		0x0e
18641480Smckusick #define BR_9600		0x0f
18741480Smckusick #define BR_19200	0x10
18841480Smckusick #define BR_38400	0x11
18941480Smckusick 
19041480Smckusick /* modem input register */
19141480Smckusick #define	MI_CTS		0x08
19241480Smckusick #define	MI_DM		0x04
19341480Smckusick #define	MI_CD		0x02
19441480Smckusick #define	MI_RI		0x01
19541480Smckusick 
19641480Smckusick /* modem output register */
19741480Smckusick #define	MO_SR		0x04
19841480Smckusick #define	MO_DTR		0x02
19941480Smckusick #define	MO_RTS		0x01
20041480Smckusick #define	MO_ON		((MO_DTR) | (MO_RTS))
20141480Smckusick #define	MO_OFF		0x00
20241480Smckusick 
20341480Smckusick /* cmd-tab values, write */
20441480Smckusick #define CT_CON		0x1	/* configuration change */
20541480Smckusick #define CT_TX		0x2	/* transmit buffer not empty */
20641480Smckusick #define CT_BRK		0x4	/* toggle BREAK */
20741480Smckusick 
20841480Smckusick /* icr-tab values, read */
20941480Smckusick #define IT_TX		0x1	/* transmit buffer empty */
21041480Smckusick #define IT_SPEC		0x2	/* special character received */
21141480Smckusick 
21241480Smckusick /* data errors */
21341480Smckusick #define RD_OVF		0x08
21441480Smckusick #define RD_BD		0x10
21541480Smckusick #define RD_PE		0x20
21641480Smckusick #define RD_OE		0x40
21741480Smckusick #define RD_FE		0x80
21841480Smckusick #define RD_MASK		0xf8
21941480Smckusick 
22041480Smckusick /* Transmit/Receive masks */
22141480Smckusick #define TX_MASK		0x0f
22241480Smckusick #define RX_MASK		0xff
22341480Smckusick 
22441480Smckusick /*
22543418Shibler  * WARNING: Serial console is assumed to be the lowest select-code card
22643418Shibler  * and that card must be logical unit 0 in the kernel.  Also, CONUNIT must
22743418Shibler  * be 1, the port affected by the REMOTE/LOCAL switch.
22841480Smckusick  */
22941480Smckusick #define CONUNIT	(1)
230