141480Smckusick /* 241480Smckusick * Copyright (c) 1982, 1986, 1990 Regents of the University of California. 341480Smckusick * All rights reserved. 441480Smckusick * 541480Smckusick * %sccs.include.redist.c% 641480Smckusick * 7*44318Shibler * @(#)dcareg.h 7.2 (Berkeley) 06/27/90 841480Smckusick */ 941480Smckusick 1041480Smckusick struct dcadevice { 1141480Smckusick u_char dca_pad0; 1241480Smckusick volatile u_char dca_irid; 1341480Smckusick volatile short dca_ic; 1441480Smckusick volatile short dca_ocbrc; 1541480Smckusick volatile short dca_lcsm; 1641480Smckusick short dca_pad1[4]; 1741480Smckusick u_char dca_pad2; 1841480Smckusick volatile u_char dca_data; 1941480Smckusick volatile short dca_ier; 20*44318Shibler u_char dca_pad4; 21*44318Shibler volatile u_char dca_iir; 2241480Smckusick volatile short dca_cfcr; 2341480Smckusick volatile short dca_mcr; 2441480Smckusick volatile short dca_lsr; 2541480Smckusick u_char dca_pad3; 2641480Smckusick volatile u_char dca_msr; 2741480Smckusick }; 2841480Smckusick 2941480Smckusick /* interface reset/id */ 3041480Smckusick #define DCAID0 0x02 3141480Smckusick #define DCAREMID0 0x82 3241480Smckusick #define DCAID1 0x42 3341480Smckusick #define DCAREMID1 0xC2 3441480Smckusick 3541480Smckusick /* interrupt control */ 3641480Smckusick #define DCAIPL(x) ((((x) >> 4) & 3) + 3) 3741480Smckusick #define IC_IR 0x40 3841480Smckusick #define IC_IE 0x80 3941480Smckusick 4041480Smckusick /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ 4141480Smckusick #define DCABRD(x) (153600 / (x)) 4241480Smckusick 4341480Smckusick /* interrupt enable register */ 4441480Smckusick #define IER_ERXRDY 0x1 4541480Smckusick #define IER_ETXRDY 0x2 4641480Smckusick #define IER_ERLS 0x4 4741480Smckusick #define IER_EMSC 0x8 4841480Smckusick 4941480Smckusick /* interrupt identification register */ 5041480Smckusick #define IIR_NOPEND 0x1 5141480Smckusick #define IIR_IMASK 0x6 5241480Smckusick #define IIR_RLS 6 5341480Smckusick #define IIR_RXRDY 4 5441480Smckusick #define IIR_TXRDY 2 5541480Smckusick #define IIR_MLSC 0 5641480Smckusick 5741480Smckusick /* character format control register */ 5841480Smckusick #define CFCR_DLAB 0x80 5941480Smckusick #define CFCR_SBREAK 0x40 6041480Smckusick #define CFCR_PZERO 0x30 6141480Smckusick #define CFCR_PONE 0x20 6241480Smckusick #define CFCR_PEVEN 0x10 6341480Smckusick #define CFCR_PODD 0x00 6441480Smckusick #define CFCR_PENAB 0x08 6541480Smckusick #define CFCR_STOPB 0x04 6641480Smckusick #define CFCR_8BITS 0x03 6741480Smckusick #define CFCR_7BITS 0x02 6841480Smckusick #define CFCR_6BITS 0x01 6941480Smckusick #define CFCR_5BITS 0x00 7041480Smckusick 7141480Smckusick /* modem control register */ 7241480Smckusick #define MCR_LOOPBACK 0x10 7341480Smckusick #define MCR_SRTS 0x08 7441480Smckusick #define MCR_DRS 0x04 7541480Smckusick #define MCR_RTS 0x02 7641480Smckusick #define MCR_DTR 0x01 7741480Smckusick 7841480Smckusick /* line status register */ 7941480Smckusick #define LSR_TSRE 0x40 8041480Smckusick #define LSR_TXRDY 0x20 8141480Smckusick #define LSR_BI 0x10 8241480Smckusick #define LSR_FE 0x08 8341480Smckusick #define LSR_PE 0x04 8441480Smckusick #define LSR_OE 0x02 8541480Smckusick #define LSR_RXRDY 0x01 8641480Smckusick 8741480Smckusick /* modem status register */ 8841480Smckusick #define MSR_DCD 0x80 8941480Smckusick #define MSR_RI 0x40 9041480Smckusick #define MSR_DSR 0x20 9141480Smckusick #define MSR_CTS 0x10 92*44318Shibler #define MSR_DDCD 0x08 9341480Smckusick #define MSR_TERI 0x04 9441480Smckusick #define MSR_DDSR 0x02 95*44318Shibler #define MSR_DCTS 0x01 9641480Smckusick 9741480Smckusick /* 9841480Smckusick * WARNING: Serial console is assumed to be at SC9 9941480Smckusick * and CONUNIT must be 0. 10041480Smckusick */ 10141480Smckusick #define CONADDR ((struct dcadevice *)(IOV(EXTIOBASE + (9 * IOCARDSIZE)))) 10241480Smckusick #define CONUNIT (0) 103