1*41480Smckusick /* 2*41480Smckusick * Copyright (c) 1982, 1986, 1990 Regents of the University of California. 3*41480Smckusick * All rights reserved. 4*41480Smckusick * 5*41480Smckusick * %sccs.include.redist.c% 6*41480Smckusick * 7*41480Smckusick * @(#)dcareg.h 7.1 (Berkeley) 05/08/90 8*41480Smckusick */ 9*41480Smckusick 10*41480Smckusick struct dcadevice { 11*41480Smckusick u_char dca_pad0; 12*41480Smckusick volatile u_char dca_irid; 13*41480Smckusick volatile short dca_ic; 14*41480Smckusick volatile short dca_ocbrc; 15*41480Smckusick volatile short dca_lcsm; 16*41480Smckusick short dca_pad1[4]; 17*41480Smckusick u_char dca_pad2; 18*41480Smckusick volatile u_char dca_data; 19*41480Smckusick volatile short dca_ier; 20*41480Smckusick volatile short dca_iir; 21*41480Smckusick volatile short dca_cfcr; 22*41480Smckusick volatile short dca_mcr; 23*41480Smckusick volatile short dca_lsr; 24*41480Smckusick u_char dca_pad3; 25*41480Smckusick volatile u_char dca_msr; 26*41480Smckusick }; 27*41480Smckusick 28*41480Smckusick /* interface reset/id */ 29*41480Smckusick #define DCAID0 0x02 30*41480Smckusick #define DCAREMID0 0x82 31*41480Smckusick #define DCAID1 0x42 32*41480Smckusick #define DCAREMID1 0xC2 33*41480Smckusick 34*41480Smckusick /* interrupt control */ 35*41480Smckusick #define DCAIPL(x) ((((x) >> 4) & 3) + 3) 36*41480Smckusick #define IC_IR 0x40 37*41480Smckusick #define IC_IE 0x80 38*41480Smckusick 39*41480Smckusick /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ 40*41480Smckusick #define DCABRD(x) (153600 / (x)) 41*41480Smckusick 42*41480Smckusick /* interrupt enable register */ 43*41480Smckusick #define IER_ERXRDY 0x1 44*41480Smckusick #define IER_ETXRDY 0x2 45*41480Smckusick #define IER_ERLS 0x4 46*41480Smckusick #define IER_EMSC 0x8 47*41480Smckusick 48*41480Smckusick /* interrupt identification register */ 49*41480Smckusick #define IIR_NOPEND 0x1 50*41480Smckusick #define IIR_IMASK 0x6 51*41480Smckusick #define IIR_RLS 6 52*41480Smckusick #define IIR_RXRDY 4 53*41480Smckusick #define IIR_TXRDY 2 54*41480Smckusick #define IIR_MLSC 0 55*41480Smckusick 56*41480Smckusick /* character format control register */ 57*41480Smckusick #define CFCR_DLAB 0x80 58*41480Smckusick #define CFCR_SBREAK 0x40 59*41480Smckusick #define CFCR_PZERO 0x30 60*41480Smckusick #define CFCR_PONE 0x20 61*41480Smckusick #define CFCR_PEVEN 0x10 62*41480Smckusick #define CFCR_PODD 0x00 63*41480Smckusick #define CFCR_PENAB 0x08 64*41480Smckusick #define CFCR_STOPB 0x04 65*41480Smckusick #define CFCR_8BITS 0x03 66*41480Smckusick #define CFCR_7BITS 0x02 67*41480Smckusick #define CFCR_6BITS 0x01 68*41480Smckusick #define CFCR_5BITS 0x00 69*41480Smckusick 70*41480Smckusick /* modem control register */ 71*41480Smckusick #define MCR_LOOPBACK 0x10 72*41480Smckusick #define MCR_SRTS 0x08 73*41480Smckusick #define MCR_DRS 0x04 74*41480Smckusick #define MCR_RTS 0x02 75*41480Smckusick #define MCR_DTR 0x01 76*41480Smckusick 77*41480Smckusick /* line status register */ 78*41480Smckusick #define LSR_TSRE 0x40 79*41480Smckusick #define LSR_TXRDY 0x20 80*41480Smckusick #define LSR_BI 0x10 81*41480Smckusick #define LSR_FE 0x08 82*41480Smckusick #define LSR_PE 0x04 83*41480Smckusick #define LSR_OE 0x02 84*41480Smckusick #define LSR_RXRDY 0x01 85*41480Smckusick 86*41480Smckusick /* modem status register */ 87*41480Smckusick #define MSR_DCD 0x80 88*41480Smckusick #define MSR_RI 0x40 89*41480Smckusick #define MSR_DSR 0x20 90*41480Smckusick #define MSR_CTS 0x10 91*41480Smckusick #define MSR_CCD 0x08 92*41480Smckusick #define MSR_TERI 0x04 93*41480Smckusick #define MSR_DDSR 0x02 94*41480Smckusick #define MSR_CCTS 0x01 95*41480Smckusick 96*41480Smckusick /* 97*41480Smckusick * WARNING: Serial console is assumed to be at SC9 98*41480Smckusick * and CONUNIT must be 0. 99*41480Smckusick */ 100*41480Smckusick #define CONADDR ((struct dcadevice *)(IOV(EXTIOBASE + (9 * IOCARDSIZE)))) 101*41480Smckusick #define CONUNIT (0) 102