1*9593dc34Smglocker/* $OpenBSD: divsi3.S,v 1.7 2024/09/04 07:54:52 mglocker Exp $ */ 27c0511a1Sdrahn/* $NetBSD: divsi3.S,v 1.2 2001/11/13 20:06:40 chris Exp $ */ 37c0511a1Sdrahn 47c0511a1Sdrahn/* 57c0511a1Sdrahn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 67c0511a1Sdrahn * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 77c0511a1Sdrahn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 87c0511a1Sdrahn * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 97c0511a1Sdrahn * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 107c0511a1Sdrahn * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 117c0511a1Sdrahn * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 127c0511a1Sdrahn * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 137c0511a1Sdrahn * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 147c0511a1Sdrahn * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 157c0511a1Sdrahn * SUCH DAMAGE. 167c0511a1Sdrahn */ 177c0511a1Sdrahn 187c0511a1Sdrahn#include <machine/asm.h> 197c0511a1Sdrahn 207c0511a1Sdrahn/* 217c0511a1Sdrahn * stack is aligned as there's a possibility of branching to L_overflow 227c0511a1Sdrahn * which makes a C call 237c0511a1Sdrahn */ 247c0511a1Sdrahn 257c0511a1SdrahnENTRY(__umodsi3) 267c0511a1Sdrahn stmfd sp!, {lr} 277c0511a1Sdrahn sub sp, sp, #4 /* align stack */ 287c0511a1Sdrahn bl L_udivide 297c0511a1Sdrahn add sp, sp, #4 /* unalign stack */ 307c0511a1Sdrahn mov r0, r1 317c0511a1Sdrahn ldmfd sp!, {pc} 327c0511a1Sdrahn 337c0511a1SdrahnENTRY(__modsi3) 347c0511a1Sdrahn stmfd sp!, {lr} 357c0511a1Sdrahn sub sp, sp, #4 /* align stack */ 367c0511a1Sdrahn bl L_divide 377c0511a1Sdrahn add sp, sp, #4 /* unalign stack */ 387c0511a1Sdrahn mov r0, r1 397c0511a1Sdrahn ldmfd sp!, {pc} 407c0511a1Sdrahn 417c0511a1SdrahnL_overflow: 427c0511a1Sdrahn#if !defined(_KERNEL) && !defined(_STANDALONE) 437c0511a1Sdrahn mov r0, #8 /* SIGFPE */ 4481621933Sguenther bl PIC_SYM(raise, PLT) /* raise it */ 457c0511a1Sdrahn mov r0, #0 467c0511a1Sdrahn#else 477c0511a1Sdrahn /* XXX should cause a fatal error */ 487c0511a1Sdrahn mvn r0, #0 497c0511a1Sdrahn#endif 507c0511a1Sdrahn mov pc, lr 517c0511a1Sdrahn 527c0511a1SdrahnENTRY(__udivsi3) 537c0511a1SdrahnL_udivide: /* r0 = r0 / r1; r1 = r0 % r1 */ 547c0511a1Sdrahn eor r0, r1, r0 557c0511a1Sdrahn eor r1, r0, r1 567c0511a1Sdrahn eor r0, r1, r0 577c0511a1Sdrahn /* r0 = r1 / r0; r1 = r1 % r0 */ 587c0511a1Sdrahn cmp r0, #1 597c0511a1Sdrahn bcc L_overflow 607c0511a1Sdrahn beq L_divide_l0 617c0511a1Sdrahn mov ip, #0 627c0511a1Sdrahn movs r1, r1 637c0511a1Sdrahn bpl L_divide_l1 647c0511a1Sdrahn orr ip, ip, #0x20000000 /* ip bit 0x20000000 = -ve r1 */ 657c0511a1Sdrahn movs r1, r1, lsr #1 667c0511a1Sdrahn orrcs ip, ip, #0x10000000 /* ip bit 0x10000000 = bit 0 of r1 */ 677c0511a1Sdrahn b L_divide_l1 687c0511a1Sdrahn 697c0511a1SdrahnL_divide_l0: /* r0 == 1 */ 707c0511a1Sdrahn mov r0, r1 717c0511a1Sdrahn mov r1, #0 727c0511a1Sdrahn mov pc, lr 737c0511a1Sdrahn 747c0511a1SdrahnENTRY(__divsi3) 757c0511a1SdrahnL_divide: /* r0 = r0 / r1; r1 = r0 % r1 */ 767c0511a1Sdrahn eor r0, r1, r0 777c0511a1Sdrahn eor r1, r0, r1 787c0511a1Sdrahn eor r0, r1, r0 797c0511a1Sdrahn /* r0 = r1 / r0; r1 = r1 % r0 */ 807c0511a1Sdrahn cmp r0, #1 817c0511a1Sdrahn bcc L_overflow 827c0511a1Sdrahn beq L_divide_l0 837c0511a1Sdrahn ands ip, r0, #0x80000000 847c0511a1Sdrahn rsbmi r0, r0, #0 857c0511a1Sdrahn ands r2, r1, #0x80000000 867c0511a1Sdrahn eor ip, ip, r2 877c0511a1Sdrahn rsbmi r1, r1, #0 887c0511a1Sdrahn orr ip, r2, ip, lsr #1 /* ip bit 0x40000000 = -ve division */ 897c0511a1Sdrahn /* ip bit 0x80000000 = -ve remainder */ 907c0511a1Sdrahn 917c0511a1SdrahnL_divide_l1: 927c0511a1Sdrahn mov r2, #1 937c0511a1Sdrahn mov r3, #0 947c0511a1Sdrahn 957c0511a1Sdrahn /* 967c0511a1Sdrahn * If the highest bit of the dividend is set, we have to be 977c0511a1Sdrahn * careful when shifting the divisor. Test this. 987c0511a1Sdrahn */ 997c0511a1Sdrahn movs r1,r1 1007c0511a1Sdrahn bpl L_old_code 1017c0511a1Sdrahn 1027c0511a1Sdrahn /* 1037c0511a1Sdrahn * At this point, the highest bit of r1 is known to be set. 1047c0511a1Sdrahn * We abuse this below in the tst instructions. 1057c0511a1Sdrahn */ 1067c0511a1Sdrahn tst r1, r0 /*, lsl #0 */ 1077c0511a1Sdrahn bmi L_divide_b1 1087c0511a1Sdrahn tst r1, r0, lsl #1 1097c0511a1Sdrahn bmi L_divide_b2 1107c0511a1Sdrahn tst r1, r0, lsl #2 1117c0511a1Sdrahn bmi L_divide_b3 1127c0511a1Sdrahn tst r1, r0, lsl #3 1137c0511a1Sdrahn bmi L_divide_b4 1147c0511a1Sdrahn tst r1, r0, lsl #4 1157c0511a1Sdrahn bmi L_divide_b5 1167c0511a1Sdrahn tst r1, r0, lsl #5 1177c0511a1Sdrahn bmi L_divide_b6 1187c0511a1Sdrahn tst r1, r0, lsl #6 1197c0511a1Sdrahn bmi L_divide_b7 1207c0511a1Sdrahn tst r1, r0, lsl #7 1217c0511a1Sdrahn bmi L_divide_b8 1227c0511a1Sdrahn tst r1, r0, lsl #8 1237c0511a1Sdrahn bmi L_divide_b9 1247c0511a1Sdrahn tst r1, r0, lsl #9 1257c0511a1Sdrahn bmi L_divide_b10 1267c0511a1Sdrahn tst r1, r0, lsl #10 1277c0511a1Sdrahn bmi L_divide_b11 1287c0511a1Sdrahn tst r1, r0, lsl #11 1297c0511a1Sdrahn bmi L_divide_b12 1307c0511a1Sdrahn tst r1, r0, lsl #12 1317c0511a1Sdrahn bmi L_divide_b13 1327c0511a1Sdrahn tst r1, r0, lsl #13 1337c0511a1Sdrahn bmi L_divide_b14 1347c0511a1Sdrahn tst r1, r0, lsl #14 1357c0511a1Sdrahn bmi L_divide_b15 1367c0511a1Sdrahn tst r1, r0, lsl #15 1377c0511a1Sdrahn bmi L_divide_b16 1387c0511a1Sdrahn tst r1, r0, lsl #16 1397c0511a1Sdrahn bmi L_divide_b17 1407c0511a1Sdrahn tst r1, r0, lsl #17 1417c0511a1Sdrahn bmi L_divide_b18 1427c0511a1Sdrahn tst r1, r0, lsl #18 1437c0511a1Sdrahn bmi L_divide_b19 1447c0511a1Sdrahn tst r1, r0, lsl #19 1457c0511a1Sdrahn bmi L_divide_b20 1467c0511a1Sdrahn tst r1, r0, lsl #20 1477c0511a1Sdrahn bmi L_divide_b21 1487c0511a1Sdrahn tst r1, r0, lsl #21 1497c0511a1Sdrahn bmi L_divide_b22 1507c0511a1Sdrahn tst r1, r0, lsl #22 1517c0511a1Sdrahn bmi L_divide_b23 1527c0511a1Sdrahn tst r1, r0, lsl #23 1537c0511a1Sdrahn bmi L_divide_b24 1547c0511a1Sdrahn tst r1, r0, lsl #24 1557c0511a1Sdrahn bmi L_divide_b25 1567c0511a1Sdrahn tst r1, r0, lsl #25 1577c0511a1Sdrahn bmi L_divide_b26 1587c0511a1Sdrahn tst r1, r0, lsl #26 1597c0511a1Sdrahn bmi L_divide_b27 1607c0511a1Sdrahn tst r1, r0, lsl #27 1617c0511a1Sdrahn bmi L_divide_b28 1627c0511a1Sdrahn tst r1, r0, lsl #28 1637c0511a1Sdrahn bmi L_divide_b29 1647c0511a1Sdrahn tst r1, r0, lsl #29 1657c0511a1Sdrahn bmi L_divide_b30 1667c0511a1Sdrahn tst r1, r0, lsl #30 1677c0511a1Sdrahn bmi L_divide_b31 1687c0511a1Sdrahn/* 1697c0511a1Sdrahn * instead of: 1707c0511a1Sdrahn * tst r1, r0, lsl #31 1717c0511a1Sdrahn * bmi L_divide_b32 1727c0511a1Sdrahn */ 1737c0511a1Sdrahn b L_divide_b32 1747c0511a1Sdrahn 1757c0511a1SdrahnL_old_code: 1767c0511a1Sdrahn cmp r1, r0 1777c0511a1Sdrahn bcc L_divide_b0 1787c0511a1Sdrahn cmp r1, r0, lsl #1 1797c0511a1Sdrahn bcc L_divide_b1 1807c0511a1Sdrahn cmp r1, r0, lsl #2 1817c0511a1Sdrahn bcc L_divide_b2 1827c0511a1Sdrahn cmp r1, r0, lsl #3 1837c0511a1Sdrahn bcc L_divide_b3 1847c0511a1Sdrahn cmp r1, r0, lsl #4 1857c0511a1Sdrahn bcc L_divide_b4 1867c0511a1Sdrahn cmp r1, r0, lsl #5 1877c0511a1Sdrahn bcc L_divide_b5 1887c0511a1Sdrahn cmp r1, r0, lsl #6 1897c0511a1Sdrahn bcc L_divide_b6 1907c0511a1Sdrahn cmp r1, r0, lsl #7 1917c0511a1Sdrahn bcc L_divide_b7 1927c0511a1Sdrahn cmp r1, r0, lsl #8 1937c0511a1Sdrahn bcc L_divide_b8 1947c0511a1Sdrahn cmp r1, r0, lsl #9 1957c0511a1Sdrahn bcc L_divide_b9 1967c0511a1Sdrahn cmp r1, r0, lsl #10 1977c0511a1Sdrahn bcc L_divide_b10 1987c0511a1Sdrahn cmp r1, r0, lsl #11 1997c0511a1Sdrahn bcc L_divide_b11 2007c0511a1Sdrahn cmp r1, r0, lsl #12 2017c0511a1Sdrahn bcc L_divide_b12 2027c0511a1Sdrahn cmp r1, r0, lsl #13 2037c0511a1Sdrahn bcc L_divide_b13 2047c0511a1Sdrahn cmp r1, r0, lsl #14 2057c0511a1Sdrahn bcc L_divide_b14 2067c0511a1Sdrahn cmp r1, r0, lsl #15 2077c0511a1Sdrahn bcc L_divide_b15 2087c0511a1Sdrahn cmp r1, r0, lsl #16 2097c0511a1Sdrahn bcc L_divide_b16 2107c0511a1Sdrahn cmp r1, r0, lsl #17 2117c0511a1Sdrahn bcc L_divide_b17 2127c0511a1Sdrahn cmp r1, r0, lsl #18 2137c0511a1Sdrahn bcc L_divide_b18 2147c0511a1Sdrahn cmp r1, r0, lsl #19 2157c0511a1Sdrahn bcc L_divide_b19 2167c0511a1Sdrahn cmp r1, r0, lsl #20 2177c0511a1Sdrahn bcc L_divide_b20 2187c0511a1Sdrahn cmp r1, r0, lsl #21 2197c0511a1Sdrahn bcc L_divide_b21 2207c0511a1Sdrahn cmp r1, r0, lsl #22 2217c0511a1Sdrahn bcc L_divide_b22 2227c0511a1Sdrahn cmp r1, r0, lsl #23 2237c0511a1Sdrahn bcc L_divide_b23 2247c0511a1Sdrahn cmp r1, r0, lsl #24 2257c0511a1Sdrahn bcc L_divide_b24 2267c0511a1Sdrahn cmp r1, r0, lsl #25 2277c0511a1Sdrahn bcc L_divide_b25 2287c0511a1Sdrahn cmp r1, r0, lsl #26 2297c0511a1Sdrahn bcc L_divide_b26 2307c0511a1Sdrahn cmp r1, r0, lsl #27 2317c0511a1Sdrahn bcc L_divide_b27 2327c0511a1Sdrahn cmp r1, r0, lsl #28 2337c0511a1Sdrahn bcc L_divide_b28 2347c0511a1Sdrahn cmp r1, r0, lsl #29 2357c0511a1Sdrahn bcc L_divide_b29 2367c0511a1Sdrahn cmp r1, r0, lsl #30 2377c0511a1Sdrahn bcc L_divide_b30 2387c0511a1SdrahnL_divide_b32: 2397c0511a1Sdrahn cmp r1, r0, lsl #31 2407c0511a1Sdrahn subhs r1, r1,r0, lsl #31 2417c0511a1Sdrahn addhs r3, r3,r2, lsl #31 2427c0511a1SdrahnL_divide_b31: 2437c0511a1Sdrahn cmp r1, r0, lsl #30 2447c0511a1Sdrahn subhs r1, r1,r0, lsl #30 2457c0511a1Sdrahn addhs r3, r3,r2, lsl #30 2467c0511a1SdrahnL_divide_b30: 2477c0511a1Sdrahn cmp r1, r0, lsl #29 2487c0511a1Sdrahn subhs r1, r1,r0, lsl #29 2497c0511a1Sdrahn addhs r3, r3,r2, lsl #29 2507c0511a1SdrahnL_divide_b29: 2517c0511a1Sdrahn cmp r1, r0, lsl #28 2527c0511a1Sdrahn subhs r1, r1,r0, lsl #28 2537c0511a1Sdrahn addhs r3, r3,r2, lsl #28 2547c0511a1SdrahnL_divide_b28: 2557c0511a1Sdrahn cmp r1, r0, lsl #27 2567c0511a1Sdrahn subhs r1, r1,r0, lsl #27 2577c0511a1Sdrahn addhs r3, r3,r2, lsl #27 2587c0511a1SdrahnL_divide_b27: 2597c0511a1Sdrahn cmp r1, r0, lsl #26 2607c0511a1Sdrahn subhs r1, r1,r0, lsl #26 2617c0511a1Sdrahn addhs r3, r3,r2, lsl #26 2627c0511a1SdrahnL_divide_b26: 2637c0511a1Sdrahn cmp r1, r0, lsl #25 2647c0511a1Sdrahn subhs r1, r1,r0, lsl #25 2657c0511a1Sdrahn addhs r3, r3,r2, lsl #25 2667c0511a1SdrahnL_divide_b25: 2677c0511a1Sdrahn cmp r1, r0, lsl #24 2687c0511a1Sdrahn subhs r1, r1,r0, lsl #24 2697c0511a1Sdrahn addhs r3, r3,r2, lsl #24 2707c0511a1SdrahnL_divide_b24: 2717c0511a1Sdrahn cmp r1, r0, lsl #23 2727c0511a1Sdrahn subhs r1, r1,r0, lsl #23 2737c0511a1Sdrahn addhs r3, r3,r2, lsl #23 2747c0511a1SdrahnL_divide_b23: 2757c0511a1Sdrahn cmp r1, r0, lsl #22 2767c0511a1Sdrahn subhs r1, r1,r0, lsl #22 2777c0511a1Sdrahn addhs r3, r3,r2, lsl #22 2787c0511a1SdrahnL_divide_b22: 2797c0511a1Sdrahn cmp r1, r0, lsl #21 2807c0511a1Sdrahn subhs r1, r1,r0, lsl #21 2817c0511a1Sdrahn addhs r3, r3,r2, lsl #21 2827c0511a1SdrahnL_divide_b21: 2837c0511a1Sdrahn cmp r1, r0, lsl #20 2847c0511a1Sdrahn subhs r1, r1,r0, lsl #20 2857c0511a1Sdrahn addhs r3, r3,r2, lsl #20 2867c0511a1SdrahnL_divide_b20: 2877c0511a1Sdrahn cmp r1, r0, lsl #19 2887c0511a1Sdrahn subhs r1, r1,r0, lsl #19 2897c0511a1Sdrahn addhs r3, r3,r2, lsl #19 2907c0511a1SdrahnL_divide_b19: 2917c0511a1Sdrahn cmp r1, r0, lsl #18 2927c0511a1Sdrahn subhs r1, r1,r0, lsl #18 2937c0511a1Sdrahn addhs r3, r3,r2, lsl #18 2947c0511a1SdrahnL_divide_b18: 2957c0511a1Sdrahn cmp r1, r0, lsl #17 2967c0511a1Sdrahn subhs r1, r1,r0, lsl #17 2977c0511a1Sdrahn addhs r3, r3,r2, lsl #17 2987c0511a1SdrahnL_divide_b17: 2997c0511a1Sdrahn cmp r1, r0, lsl #16 3007c0511a1Sdrahn subhs r1, r1,r0, lsl #16 3017c0511a1Sdrahn addhs r3, r3,r2, lsl #16 3027c0511a1SdrahnL_divide_b16: 3037c0511a1Sdrahn cmp r1, r0, lsl #15 3047c0511a1Sdrahn subhs r1, r1,r0, lsl #15 3057c0511a1Sdrahn addhs r3, r3,r2, lsl #15 3067c0511a1SdrahnL_divide_b15: 3077c0511a1Sdrahn cmp r1, r0, lsl #14 3087c0511a1Sdrahn subhs r1, r1,r0, lsl #14 3097c0511a1Sdrahn addhs r3, r3,r2, lsl #14 3107c0511a1SdrahnL_divide_b14: 3117c0511a1Sdrahn cmp r1, r0, lsl #13 3127c0511a1Sdrahn subhs r1, r1,r0, lsl #13 3137c0511a1Sdrahn addhs r3, r3,r2, lsl #13 3147c0511a1SdrahnL_divide_b13: 3157c0511a1Sdrahn cmp r1, r0, lsl #12 3167c0511a1Sdrahn subhs r1, r1,r0, lsl #12 3177c0511a1Sdrahn addhs r3, r3,r2, lsl #12 3187c0511a1SdrahnL_divide_b12: 3197c0511a1Sdrahn cmp r1, r0, lsl #11 3207c0511a1Sdrahn subhs r1, r1,r0, lsl #11 3217c0511a1Sdrahn addhs r3, r3,r2, lsl #11 3227c0511a1SdrahnL_divide_b11: 3237c0511a1Sdrahn cmp r1, r0, lsl #10 3247c0511a1Sdrahn subhs r1, r1,r0, lsl #10 3257c0511a1Sdrahn addhs r3, r3,r2, lsl #10 3267c0511a1SdrahnL_divide_b10: 3277c0511a1Sdrahn cmp r1, r0, lsl #9 3287c0511a1Sdrahn subhs r1, r1,r0, lsl #9 3297c0511a1Sdrahn addhs r3, r3,r2, lsl #9 3307c0511a1SdrahnL_divide_b9: 3317c0511a1Sdrahn cmp r1, r0, lsl #8 3327c0511a1Sdrahn subhs r1, r1,r0, lsl #8 3337c0511a1Sdrahn addhs r3, r3,r2, lsl #8 3347c0511a1SdrahnL_divide_b8: 3357c0511a1Sdrahn cmp r1, r0, lsl #7 3367c0511a1Sdrahn subhs r1, r1,r0, lsl #7 3377c0511a1Sdrahn addhs r3, r3,r2, lsl #7 3387c0511a1SdrahnL_divide_b7: 3397c0511a1Sdrahn cmp r1, r0, lsl #6 3407c0511a1Sdrahn subhs r1, r1,r0, lsl #6 3417c0511a1Sdrahn addhs r3, r3,r2, lsl #6 3427c0511a1SdrahnL_divide_b6: 3437c0511a1Sdrahn cmp r1, r0, lsl #5 3447c0511a1Sdrahn subhs r1, r1,r0, lsl #5 3457c0511a1Sdrahn addhs r3, r3,r2, lsl #5 3467c0511a1SdrahnL_divide_b5: 3477c0511a1Sdrahn cmp r1, r0, lsl #4 3487c0511a1Sdrahn subhs r1, r1,r0, lsl #4 3497c0511a1Sdrahn addhs r3, r3,r2, lsl #4 3507c0511a1SdrahnL_divide_b4: 3517c0511a1Sdrahn cmp r1, r0, lsl #3 3527c0511a1Sdrahn subhs r1, r1,r0, lsl #3 3537c0511a1Sdrahn addhs r3, r3,r2, lsl #3 3547c0511a1SdrahnL_divide_b3: 3557c0511a1Sdrahn cmp r1, r0, lsl #2 3567c0511a1Sdrahn subhs r1, r1,r0, lsl #2 3577c0511a1Sdrahn addhs r3, r3,r2, lsl #2 3587c0511a1SdrahnL_divide_b2: 3597c0511a1Sdrahn cmp r1, r0, lsl #1 3607c0511a1Sdrahn subhs r1, r1,r0, lsl #1 3617c0511a1Sdrahn addhs r3, r3,r2, lsl #1 3627c0511a1SdrahnL_divide_b1: 3637c0511a1Sdrahn cmp r1, r0 3647c0511a1Sdrahn subhs r1, r1, r0 3657c0511a1Sdrahn addhs r3, r3, r2 3667c0511a1SdrahnL_divide_b0: 3677c0511a1Sdrahn 3687c0511a1Sdrahn tst ip, #0x20000000 3697c0511a1Sdrahn bne L_udivide_l1 3707c0511a1Sdrahn mov r0, r3 3717c0511a1Sdrahn cmp ip, #0 3727c0511a1Sdrahn rsbmi r1, r1, #0 3737c0511a1Sdrahn movs ip, ip, lsl #1 3747c0511a1Sdrahn bicmi r0, r0, #0x80000000 /* Fix in case we divided 0x80000000 */ 3757c0511a1Sdrahn rsbmi r0, r0, #0 3767c0511a1Sdrahn mov pc, lr 3777c0511a1Sdrahn 3787c0511a1SdrahnL_udivide_l1: 3797c0511a1Sdrahn tst ip, #0x10000000 3807c0511a1Sdrahn mov r1, r1, lsl #1 3817c0511a1Sdrahn orrne r1, r1, #1 3827c0511a1Sdrahn mov r3, r3, lsl #1 3837c0511a1Sdrahn cmp r1, r0 3847c0511a1Sdrahn subhs r1, r1, r0 3857c0511a1Sdrahn addhs r3, r3, r2 3867c0511a1Sdrahn mov r0, r3 3877c0511a1Sdrahn mov pc, lr 388f25c95cdSkettenis 389f25c95cdSkettenisSTRONG_ALIAS(__aeabi_idiv, __divsi3) 390e20fadedSjsgSTRONG_ALIAS(__aeabi_idivmod, __divsi3) 391f25c95cdSkettenisSTRONG_ALIAS(__aeabi_uidiv, __udivsi3) 392e20fadedSjsgSTRONG_ALIAS(__aeabi_uidivmod, __udivsi3) 393