xref: /openbsd-src/sys/dev/pci/drm/radeon/radeon_ucode.c (revision c349dbc7938c71a30e13c1be4acc1976165f4630)
17ccd5a2cSjsg /*
27ccd5a2cSjsg  * Copyright 2014 Advanced Micro Devices, Inc.
37ccd5a2cSjsg  *
47ccd5a2cSjsg  * Permission is hereby granted, free of charge, to any person obtaining a
57ccd5a2cSjsg  * copy of this software and associated documentation files (the "Software"),
67ccd5a2cSjsg  * to deal in the Software without restriction, including without limitation
77ccd5a2cSjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
87ccd5a2cSjsg  * and/or sell copies of the Software, and to permit persons to whom the
97ccd5a2cSjsg  * Software is furnished to do so, subject to the following conditions:
107ccd5a2cSjsg  *
117ccd5a2cSjsg  * The above copyright notice and this permission notice shall be included in
127ccd5a2cSjsg  * all copies or substantial portions of the Software.
137ccd5a2cSjsg  *
147ccd5a2cSjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
157ccd5a2cSjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
167ccd5a2cSjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
177ccd5a2cSjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
187ccd5a2cSjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
197ccd5a2cSjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
207ccd5a2cSjsg  * OTHER DEALINGS IN THE SOFTWARE.
217ccd5a2cSjsg  *
227ccd5a2cSjsg  */
237ccd5a2cSjsg 
247f4dd379Sjsg #include <linux/firmware.h>
257f4dd379Sjsg #include <linux/slab.h>
267f4dd379Sjsg #include <linux/module.h>
27*c349dbc7Sjsg 
287ccd5a2cSjsg #include "radeon.h"
297ccd5a2cSjsg #include "radeon_ucode.h"
307ccd5a2cSjsg 
radeon_ucode_print_common_hdr(const struct common_firmware_header * hdr)317ccd5a2cSjsg static void radeon_ucode_print_common_hdr(const struct common_firmware_header *hdr)
327ccd5a2cSjsg {
337ccd5a2cSjsg 	DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
347ccd5a2cSjsg 	DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
357ccd5a2cSjsg 	DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
367ccd5a2cSjsg 	DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
377ccd5a2cSjsg 	DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
387ccd5a2cSjsg 	DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
397ccd5a2cSjsg 	DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
407ccd5a2cSjsg 	DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
417ccd5a2cSjsg 	DRM_DEBUG("ucode_array_offset_bytes: %u\n",
427ccd5a2cSjsg 		  le32_to_cpu(hdr->ucode_array_offset_bytes));
437ccd5a2cSjsg 	DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
447ccd5a2cSjsg }
457ccd5a2cSjsg 
radeon_ucode_print_mc_hdr(const struct common_firmware_header * hdr)467ccd5a2cSjsg void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
477ccd5a2cSjsg {
487ccd5a2cSjsg 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
497ccd5a2cSjsg 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
507ccd5a2cSjsg 
517ccd5a2cSjsg 	DRM_DEBUG("MC\n");
527ccd5a2cSjsg 	radeon_ucode_print_common_hdr(hdr);
537ccd5a2cSjsg 
547ccd5a2cSjsg 	if (version_major == 1) {
557ccd5a2cSjsg 		const struct mc_firmware_header_v1_0 *mc_hdr =
567ccd5a2cSjsg 			container_of(hdr, struct mc_firmware_header_v1_0, header);
577ccd5a2cSjsg 
587ccd5a2cSjsg 		DRM_DEBUG("io_debug_size_bytes: %u\n",
597ccd5a2cSjsg 			  le32_to_cpu(mc_hdr->io_debug_size_bytes));
607ccd5a2cSjsg 		DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
617ccd5a2cSjsg 			  le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
627ccd5a2cSjsg 	} else {
637ccd5a2cSjsg 		DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
647ccd5a2cSjsg 	}
657ccd5a2cSjsg }
667ccd5a2cSjsg 
radeon_ucode_print_smc_hdr(const struct common_firmware_header * hdr)677ccd5a2cSjsg void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
687ccd5a2cSjsg {
697ccd5a2cSjsg 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
707ccd5a2cSjsg 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
717ccd5a2cSjsg 
727ccd5a2cSjsg 	DRM_DEBUG("SMC\n");
737ccd5a2cSjsg 	radeon_ucode_print_common_hdr(hdr);
747ccd5a2cSjsg 
757ccd5a2cSjsg 	if (version_major == 1) {
767ccd5a2cSjsg 		const struct smc_firmware_header_v1_0 *smc_hdr =
777ccd5a2cSjsg 			container_of(hdr, struct smc_firmware_header_v1_0, header);
787ccd5a2cSjsg 
797ccd5a2cSjsg 		DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
807ccd5a2cSjsg 	} else {
817ccd5a2cSjsg 		DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
827ccd5a2cSjsg 	}
837ccd5a2cSjsg }
847ccd5a2cSjsg 
radeon_ucode_print_gfx_hdr(const struct common_firmware_header * hdr)857ccd5a2cSjsg void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
867ccd5a2cSjsg {
877ccd5a2cSjsg 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
887ccd5a2cSjsg 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
897ccd5a2cSjsg 
907ccd5a2cSjsg 	DRM_DEBUG("GFX\n");
917ccd5a2cSjsg 	radeon_ucode_print_common_hdr(hdr);
927ccd5a2cSjsg 
937ccd5a2cSjsg 	if (version_major == 1) {
947ccd5a2cSjsg 		const struct gfx_firmware_header_v1_0 *gfx_hdr =
957ccd5a2cSjsg 			container_of(hdr, struct gfx_firmware_header_v1_0, header);
967ccd5a2cSjsg 
977ccd5a2cSjsg 		DRM_DEBUG("ucode_feature_version: %u\n",
987ccd5a2cSjsg 			  le32_to_cpu(gfx_hdr->ucode_feature_version));
997ccd5a2cSjsg 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
1007ccd5a2cSjsg 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
1017ccd5a2cSjsg 	} else {
1027ccd5a2cSjsg 		DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
1037ccd5a2cSjsg 	}
1047ccd5a2cSjsg }
1057ccd5a2cSjsg 
radeon_ucode_print_rlc_hdr(const struct common_firmware_header * hdr)1067ccd5a2cSjsg void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
1077ccd5a2cSjsg {
1087ccd5a2cSjsg 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
1097ccd5a2cSjsg 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
1107ccd5a2cSjsg 
1117ccd5a2cSjsg 	DRM_DEBUG("RLC\n");
1127ccd5a2cSjsg 	radeon_ucode_print_common_hdr(hdr);
1137ccd5a2cSjsg 
1147ccd5a2cSjsg 	if (version_major == 1) {
1157ccd5a2cSjsg 		const struct rlc_firmware_header_v1_0 *rlc_hdr =
1167ccd5a2cSjsg 			container_of(hdr, struct rlc_firmware_header_v1_0, header);
1177ccd5a2cSjsg 
1187ccd5a2cSjsg 		DRM_DEBUG("ucode_feature_version: %u\n",
1197ccd5a2cSjsg 			  le32_to_cpu(rlc_hdr->ucode_feature_version));
1207ccd5a2cSjsg 		DRM_DEBUG("save_and_restore_offset: %u\n",
1217ccd5a2cSjsg 			  le32_to_cpu(rlc_hdr->save_and_restore_offset));
1227ccd5a2cSjsg 		DRM_DEBUG("clear_state_descriptor_offset: %u\n",
1237ccd5a2cSjsg 			  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
1247ccd5a2cSjsg 		DRM_DEBUG("avail_scratch_ram_locations: %u\n",
1257ccd5a2cSjsg 			  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
1267ccd5a2cSjsg 		DRM_DEBUG("master_pkt_description_offset: %u\n",
1277ccd5a2cSjsg 			  le32_to_cpu(rlc_hdr->master_pkt_description_offset));
1287ccd5a2cSjsg 	} else {
1297ccd5a2cSjsg 		DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
1307ccd5a2cSjsg 	}
1317ccd5a2cSjsg }
1327ccd5a2cSjsg 
radeon_ucode_print_sdma_hdr(const struct common_firmware_header * hdr)1337ccd5a2cSjsg void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
1347ccd5a2cSjsg {
1357ccd5a2cSjsg 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
1367ccd5a2cSjsg 	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
1377ccd5a2cSjsg 
1387ccd5a2cSjsg 	DRM_DEBUG("SDMA\n");
1397ccd5a2cSjsg 	radeon_ucode_print_common_hdr(hdr);
1407ccd5a2cSjsg 
1417ccd5a2cSjsg 	if (version_major == 1) {
1427ccd5a2cSjsg 		const struct sdma_firmware_header_v1_0 *sdma_hdr =
1437ccd5a2cSjsg 			container_of(hdr, struct sdma_firmware_header_v1_0, header);
1447ccd5a2cSjsg 
1457ccd5a2cSjsg 		DRM_DEBUG("ucode_feature_version: %u\n",
1467ccd5a2cSjsg 			  le32_to_cpu(sdma_hdr->ucode_feature_version));
1477ccd5a2cSjsg 		DRM_DEBUG("ucode_change_version: %u\n",
1487ccd5a2cSjsg 			  le32_to_cpu(sdma_hdr->ucode_change_version));
1497ccd5a2cSjsg 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
1507ccd5a2cSjsg 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
1517ccd5a2cSjsg 	} else {
1527ccd5a2cSjsg 		DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
1537ccd5a2cSjsg 			  version_major, version_minor);
1547ccd5a2cSjsg 	}
1557ccd5a2cSjsg }
1567ccd5a2cSjsg 
radeon_ucode_validate(const struct firmware * fw)1577ccd5a2cSjsg int radeon_ucode_validate(const struct firmware *fw)
1587ccd5a2cSjsg {
1597ccd5a2cSjsg 	const struct common_firmware_header *hdr =
1607ccd5a2cSjsg 		(const struct common_firmware_header *)fw->data;
1617ccd5a2cSjsg 
1627ccd5a2cSjsg 	if (fw->size == le32_to_cpu(hdr->size_bytes))
1637ccd5a2cSjsg 		return 0;
1647ccd5a2cSjsg 
1657ccd5a2cSjsg 	return -EINVAL;
1667ccd5a2cSjsg }
1677ccd5a2cSjsg 
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