1f005ef32Sjsg /* 2f005ef32Sjsg * Copyright © 2007 David Airlie 3f005ef32Sjsg * 4f005ef32Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5f005ef32Sjsg * copy of this software and associated documentation files (the "Software"), 6f005ef32Sjsg * to deal in the Software without restriction, including without limitation 7f005ef32Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8f005ef32Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9f005ef32Sjsg * Software is furnished to do so, subject to the following conditions: 10f005ef32Sjsg * 11f005ef32Sjsg * The above copyright notice and this permission notice (including the next 12f005ef32Sjsg * paragraph) shall be included in all copies or substantial portions of the 13f005ef32Sjsg * Software. 14f005ef32Sjsg * 15f005ef32Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16f005ef32Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17f005ef32Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18f005ef32Sjsg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19f005ef32Sjsg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20f005ef32Sjsg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21f005ef32Sjsg * DEALINGS IN THE SOFTWARE. 22f005ef32Sjsg * 23f005ef32Sjsg * Authors: 24f005ef32Sjsg * David Airlie 25f005ef32Sjsg */ 26f005ef32Sjsg 27f005ef32Sjsg #include <linux/fb.h> 28f005ef32Sjsg #include <linux/pci.h> 29f005ef32Sjsg #include <linux/pm_runtime.h> 30f005ef32Sjsg #include <linux/vga_switcheroo.h> 31f005ef32Sjsg 32f005ef32Sjsg #include <drm/drm_crtc_helper.h> 33f005ef32Sjsg #include <drm/drm_drv.h> 34f005ef32Sjsg #include <drm/drm_fb_helper.h> 35f005ef32Sjsg #include <drm/drm_fourcc.h> 36f005ef32Sjsg #include <drm/drm_framebuffer.h> 37f005ef32Sjsg #include <drm/drm_gem_framebuffer_helper.h> 38f005ef32Sjsg 39f005ef32Sjsg #include "radeon.h" 40f005ef32Sjsg 41f005ef32Sjsg static void radeon_fbdev_destroy_pinned_object(struct drm_gem_object *gobj) 42f005ef32Sjsg { 43f005ef32Sjsg struct radeon_bo *rbo = gem_to_radeon_bo(gobj); 44f005ef32Sjsg int ret; 45f005ef32Sjsg 46f005ef32Sjsg ret = radeon_bo_reserve(rbo, false); 47f005ef32Sjsg if (likely(ret == 0)) { 48f005ef32Sjsg radeon_bo_kunmap(rbo); 49f005ef32Sjsg radeon_bo_unpin(rbo); 50f005ef32Sjsg radeon_bo_unreserve(rbo); 51f005ef32Sjsg } 52f005ef32Sjsg drm_gem_object_put(gobj); 53f005ef32Sjsg } 54f005ef32Sjsg 55f005ef32Sjsg static int radeon_fbdev_create_pinned_object(struct drm_fb_helper *fb_helper, 56f005ef32Sjsg struct drm_mode_fb_cmd2 *mode_cmd, 57f005ef32Sjsg struct drm_gem_object **gobj_p) 58f005ef32Sjsg { 59f005ef32Sjsg const struct drm_format_info *info; 60f005ef32Sjsg struct radeon_device *rdev = fb_helper->dev->dev_private; 61f005ef32Sjsg struct drm_gem_object *gobj = NULL; 62f005ef32Sjsg struct radeon_bo *rbo = NULL; 63f005ef32Sjsg bool fb_tiled = false; /* useful for testing */ 64f005ef32Sjsg u32 tiling_flags = 0; 65f005ef32Sjsg int ret; 66f005ef32Sjsg int aligned_size, size; 67f005ef32Sjsg int height = mode_cmd->height; 68f005ef32Sjsg u32 cpp; 69f005ef32Sjsg 70*33a3edb1Sjsg info = drm_get_format_info(rdev_to_drm(rdev), mode_cmd); 71f005ef32Sjsg cpp = info->cpp[0]; 72f005ef32Sjsg 73f005ef32Sjsg /* need to align pitch with crtc limits */ 74f005ef32Sjsg mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, cpp, 75f005ef32Sjsg fb_tiled); 76f005ef32Sjsg 77f005ef32Sjsg if (rdev->family >= CHIP_R600) 78f005ef32Sjsg height = ALIGN(mode_cmd->height, 8); 79f005ef32Sjsg size = mode_cmd->pitches[0] * height; 80f005ef32Sjsg aligned_size = ALIGN(size, PAGE_SIZE); 81f005ef32Sjsg ret = radeon_gem_object_create(rdev, aligned_size, 0, 82f005ef32Sjsg RADEON_GEM_DOMAIN_VRAM, 83f005ef32Sjsg 0, true, &gobj); 84f005ef32Sjsg if (ret) { 85f005ef32Sjsg pr_err("failed to allocate framebuffer (%d)\n", aligned_size); 86f005ef32Sjsg return -ENOMEM; 87f005ef32Sjsg } 88f005ef32Sjsg rbo = gem_to_radeon_bo(gobj); 89f005ef32Sjsg 90f005ef32Sjsg if (fb_tiled) 91f005ef32Sjsg tiling_flags = RADEON_TILING_MACRO; 92f005ef32Sjsg 93f005ef32Sjsg #ifdef __BIG_ENDIAN 94f005ef32Sjsg switch (cpp) { 95f005ef32Sjsg case 4: 96f005ef32Sjsg tiling_flags |= RADEON_TILING_SWAP_32BIT; 97f005ef32Sjsg break; 98f005ef32Sjsg case 2: 99f005ef32Sjsg tiling_flags |= RADEON_TILING_SWAP_16BIT; 100f005ef32Sjsg break; 101f005ef32Sjsg default: 102f005ef32Sjsg break; 103f005ef32Sjsg } 104f005ef32Sjsg #endif 105f005ef32Sjsg 106f005ef32Sjsg if (tiling_flags) { 107f005ef32Sjsg ret = radeon_bo_set_tiling_flags(rbo, 108f005ef32Sjsg tiling_flags | RADEON_TILING_SURFACE, 109f005ef32Sjsg mode_cmd->pitches[0]); 110f005ef32Sjsg if (ret) 111f005ef32Sjsg dev_err(rdev->dev, "FB failed to set tiling flags\n"); 112f005ef32Sjsg } 113f005ef32Sjsg 114f005ef32Sjsg ret = radeon_bo_reserve(rbo, false); 115f005ef32Sjsg if (unlikely(ret != 0)) 116f005ef32Sjsg goto err_radeon_fbdev_destroy_pinned_object; 117f005ef32Sjsg /* Only 27 bit offset for legacy CRTC */ 118f005ef32Sjsg ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 119f005ef32Sjsg ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, 120f005ef32Sjsg NULL); 121f005ef32Sjsg if (ret) { 122f005ef32Sjsg radeon_bo_unreserve(rbo); 123f005ef32Sjsg goto err_radeon_fbdev_destroy_pinned_object; 124f005ef32Sjsg } 125f005ef32Sjsg if (fb_tiled) 126f005ef32Sjsg radeon_bo_check_tiling(rbo, 0, 0); 127f005ef32Sjsg ret = radeon_bo_kmap(rbo, NULL); 128f005ef32Sjsg radeon_bo_unreserve(rbo); 129f005ef32Sjsg if (ret) 130f005ef32Sjsg goto err_radeon_fbdev_destroy_pinned_object; 131f005ef32Sjsg 132f005ef32Sjsg *gobj_p = gobj; 133f005ef32Sjsg return 0; 134f005ef32Sjsg 135f005ef32Sjsg err_radeon_fbdev_destroy_pinned_object: 136f005ef32Sjsg radeon_fbdev_destroy_pinned_object(gobj); 137f005ef32Sjsg *gobj_p = NULL; 138f005ef32Sjsg return ret; 139f005ef32Sjsg } 140f005ef32Sjsg 141f005ef32Sjsg /* 142f005ef32Sjsg * Fbdev ops and struct fb_ops 143f005ef32Sjsg */ 144f005ef32Sjsg 145f005ef32Sjsg #ifdef __linux__ 146f005ef32Sjsg static int radeon_fbdev_fb_open(struct fb_info *info, int user) 147f005ef32Sjsg { 148f005ef32Sjsg struct drm_fb_helper *fb_helper = info->par; 149f005ef32Sjsg struct radeon_device *rdev = fb_helper->dev->dev_private; 150f005ef32Sjsg int ret; 151f005ef32Sjsg 152*33a3edb1Sjsg ret = pm_runtime_get_sync(rdev_to_drm(rdev)->dev); 153f005ef32Sjsg if (ret < 0 && ret != -EACCES) 154f005ef32Sjsg goto err_pm_runtime_mark_last_busy; 155f005ef32Sjsg 156f005ef32Sjsg return 0; 157f005ef32Sjsg 158f005ef32Sjsg err_pm_runtime_mark_last_busy: 159*33a3edb1Sjsg pm_runtime_mark_last_busy(rdev_to_drm(rdev)->dev); 160*33a3edb1Sjsg pm_runtime_put_autosuspend(rdev_to_drm(rdev)->dev); 161f005ef32Sjsg return ret; 162f005ef32Sjsg } 163f005ef32Sjsg 164f005ef32Sjsg static int radeon_fbdev_fb_release(struct fb_info *info, int user) 165f005ef32Sjsg { 166f005ef32Sjsg struct drm_fb_helper *fb_helper = info->par; 167f005ef32Sjsg struct radeon_device *rdev = fb_helper->dev->dev_private; 168f005ef32Sjsg 169*33a3edb1Sjsg pm_runtime_mark_last_busy(rdev_to_drm(rdev)->dev); 170*33a3edb1Sjsg pm_runtime_put_autosuspend(rdev_to_drm(rdev)->dev); 171f005ef32Sjsg 172f005ef32Sjsg return 0; 173f005ef32Sjsg } 174f005ef32Sjsg 175f005ef32Sjsg static void radeon_fbdev_fb_destroy(struct fb_info *info) 176f005ef32Sjsg { 177f005ef32Sjsg struct drm_fb_helper *fb_helper = info->par; 178f005ef32Sjsg struct drm_framebuffer *fb = fb_helper->fb; 179f005ef32Sjsg struct drm_gem_object *gobj = drm_gem_fb_get_obj(fb, 0); 180f005ef32Sjsg 181f005ef32Sjsg drm_fb_helper_fini(fb_helper); 182f005ef32Sjsg 183f005ef32Sjsg drm_framebuffer_unregister_private(fb); 184f005ef32Sjsg drm_framebuffer_cleanup(fb); 185f005ef32Sjsg kfree(fb); 186f005ef32Sjsg radeon_fbdev_destroy_pinned_object(gobj); 187f005ef32Sjsg 188f005ef32Sjsg drm_client_release(&fb_helper->client); 189f005ef32Sjsg drm_fb_helper_unprepare(fb_helper); 190f005ef32Sjsg kfree(fb_helper); 191f005ef32Sjsg } 192f005ef32Sjsg #endif /* __linux__ */ 193f005ef32Sjsg 194f005ef32Sjsg static const struct fb_ops radeon_fbdev_fb_ops = { 195f005ef32Sjsg #ifdef notyet 196f005ef32Sjsg .owner = THIS_MODULE, 197f005ef32Sjsg .fb_open = radeon_fbdev_fb_open, 198f005ef32Sjsg .fb_release = radeon_fbdev_fb_release, 199f005ef32Sjsg FB_DEFAULT_IOMEM_OPS, 200f005ef32Sjsg DRM_FB_HELPER_DEFAULT_OPS, 201f005ef32Sjsg .fb_destroy = radeon_fbdev_fb_destroy, 202f005ef32Sjsg #else 203f005ef32Sjsg DRM_FB_HELPER_DEFAULT_OPS, 204f005ef32Sjsg #endif 205f005ef32Sjsg }; 206f005ef32Sjsg 207f005ef32Sjsg /* 208f005ef32Sjsg * Fbdev helpers and struct drm_fb_helper_funcs 209f005ef32Sjsg */ 210f005ef32Sjsg 211f005ef32Sjsg static int radeon_fbdev_fb_helper_fb_probe(struct drm_fb_helper *fb_helper, 212f005ef32Sjsg struct drm_fb_helper_surface_size *sizes) 213f005ef32Sjsg { 214f005ef32Sjsg struct radeon_device *rdev = fb_helper->dev->dev_private; 215f005ef32Sjsg struct drm_mode_fb_cmd2 mode_cmd = { }; 216f005ef32Sjsg struct fb_info *info; 217f005ef32Sjsg struct rasops_info *ri = &rdev->ro; 218f005ef32Sjsg struct drm_gem_object *gobj; 219f005ef32Sjsg struct radeon_bo *rbo; 220f005ef32Sjsg struct drm_framebuffer *fb; 221f005ef32Sjsg int ret; 222f005ef32Sjsg unsigned long tmp; 223f005ef32Sjsg 224f005ef32Sjsg mode_cmd.width = sizes->surface_width; 225f005ef32Sjsg mode_cmd.height = sizes->surface_height; 226f005ef32Sjsg 227f005ef32Sjsg /* avivo can't scanout real 24bpp */ 228f005ef32Sjsg if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) 229f005ef32Sjsg sizes->surface_bpp = 32; 230f005ef32Sjsg 231f005ef32Sjsg mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, 232f005ef32Sjsg sizes->surface_depth); 233f005ef32Sjsg 234f005ef32Sjsg ret = radeon_fbdev_create_pinned_object(fb_helper, &mode_cmd, &gobj); 235f005ef32Sjsg if (ret) { 236f005ef32Sjsg DRM_ERROR("failed to create fbcon object %d\n", ret); 237f005ef32Sjsg return ret; 238f005ef32Sjsg } 239f005ef32Sjsg rbo = gem_to_radeon_bo(gobj); 240f005ef32Sjsg 241f005ef32Sjsg fb = kzalloc(sizeof(*fb), GFP_KERNEL); 242f005ef32Sjsg if (!fb) { 243f005ef32Sjsg ret = -ENOMEM; 244f005ef32Sjsg goto err_radeon_fbdev_destroy_pinned_object; 245f005ef32Sjsg } 246*33a3edb1Sjsg ret = radeon_framebuffer_init(rdev_to_drm(rdev), fb, &mode_cmd, gobj); 247f005ef32Sjsg if (ret) { 248f005ef32Sjsg DRM_ERROR("failed to initialize framebuffer %d\n", ret); 249f005ef32Sjsg goto err_kfree; 250f005ef32Sjsg } 251f005ef32Sjsg 252f005ef32Sjsg /* setup helper */ 253f005ef32Sjsg fb_helper->fb = fb; 254f005ef32Sjsg 255f005ef32Sjsg /* okay we have an object now allocate the framebuffer */ 256f005ef32Sjsg info = drm_fb_helper_alloc_info(fb_helper); 257f005ef32Sjsg if (IS_ERR(info)) { 258f005ef32Sjsg ret = PTR_ERR(info); 259f005ef32Sjsg goto err_drm_framebuffer_unregister_private; 260f005ef32Sjsg } 261f005ef32Sjsg 262f005ef32Sjsg info->fbops = &radeon_fbdev_fb_ops; 263f005ef32Sjsg 264f005ef32Sjsg /* radeon resume is fragile and needs a vt switch to help it along */ 265f005ef32Sjsg info->skip_vt_switch = false; 266f005ef32Sjsg 267f005ef32Sjsg drm_fb_helper_fill_info(info, fb_helper, sizes); 268f005ef32Sjsg 269f005ef32Sjsg tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; 270f005ef32Sjsg info->fix.smem_start = rdev->mc.aper_base + tmp; 271f005ef32Sjsg info->fix.smem_len = radeon_bo_size(rbo); 272f005ef32Sjsg info->screen_base = (__force void __iomem *)rbo->kptr; 273f005ef32Sjsg info->screen_size = radeon_bo_size(rbo); 274f005ef32Sjsg 275f005ef32Sjsg memset_io(info->screen_base, 0, info->screen_size); 276f005ef32Sjsg 277f005ef32Sjsg /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ 278f005ef32Sjsg 279f005ef32Sjsg DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); 280f005ef32Sjsg DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); 281f005ef32Sjsg DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); 282f005ef32Sjsg DRM_INFO("fb depth is %d\n", fb->format->depth); 283f005ef32Sjsg DRM_INFO(" pitch is %d\n", fb->pitches[0]); 284f005ef32Sjsg 285f005ef32Sjsg ri->ri_bits = rbo->kptr; 286f005ef32Sjsg ri->ri_depth = fb->format->cpp[0] * 8; 287f005ef32Sjsg ri->ri_stride = fb->pitches[0]; 288f005ef32Sjsg ri->ri_width = sizes->fb_width; 289f005ef32Sjsg ri->ri_height = sizes->fb_height; 290f005ef32Sjsg 291f005ef32Sjsg switch (fb->format->format) { 292f005ef32Sjsg case DRM_FORMAT_XRGB8888: 293f005ef32Sjsg ri->ri_rnum = 8; 294f005ef32Sjsg ri->ri_rpos = 16; 295f005ef32Sjsg ri->ri_gnum = 8; 296f005ef32Sjsg ri->ri_gpos = 8; 297f005ef32Sjsg ri->ri_bnum = 8; 298f005ef32Sjsg ri->ri_bpos = 0; 299f005ef32Sjsg break; 300f005ef32Sjsg case DRM_FORMAT_RGB565: 301f005ef32Sjsg ri->ri_rnum = 5; 302f005ef32Sjsg ri->ri_rpos = 11; 303f005ef32Sjsg ri->ri_gnum = 6; 304f005ef32Sjsg ri->ri_gpos = 5; 305f005ef32Sjsg ri->ri_bnum = 5; 306f005ef32Sjsg ri->ri_bpos = 0; 307f005ef32Sjsg break; 308f005ef32Sjsg } 309f005ef32Sjsg 310f005ef32Sjsg return 0; 311f005ef32Sjsg 312f005ef32Sjsg err_drm_framebuffer_unregister_private: 313f005ef32Sjsg fb_helper->fb = NULL; 314f005ef32Sjsg drm_framebuffer_unregister_private(fb); 315f005ef32Sjsg drm_framebuffer_cleanup(fb); 316f005ef32Sjsg err_kfree: 317f005ef32Sjsg kfree(fb); 318f005ef32Sjsg err_radeon_fbdev_destroy_pinned_object: 319f005ef32Sjsg radeon_fbdev_destroy_pinned_object(gobj); 320f005ef32Sjsg return ret; 321f005ef32Sjsg } 322f005ef32Sjsg 323f005ef32Sjsg static const struct drm_fb_helper_funcs radeon_fbdev_fb_helper_funcs = { 324f005ef32Sjsg .fb_probe = radeon_fbdev_fb_helper_fb_probe, 325f005ef32Sjsg }; 326f005ef32Sjsg 327f005ef32Sjsg /* 328f005ef32Sjsg * Fbdev client and struct drm_client_funcs 329f005ef32Sjsg */ 330f005ef32Sjsg 331f005ef32Sjsg static void radeon_fbdev_client_unregister(struct drm_client_dev *client) 332f005ef32Sjsg { 333f005ef32Sjsg struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); 334f005ef32Sjsg struct drm_device *dev = fb_helper->dev; 335f005ef32Sjsg struct radeon_device *rdev = dev->dev_private; 336f005ef32Sjsg 337f005ef32Sjsg if (fb_helper->info) { 338f005ef32Sjsg vga_switcheroo_client_fb_set(rdev->pdev, NULL); 339f005ef32Sjsg drm_helper_force_disable_all(dev); 340f005ef32Sjsg drm_fb_helper_unregister_info(fb_helper); 341f005ef32Sjsg } else { 342f005ef32Sjsg drm_client_release(&fb_helper->client); 343f005ef32Sjsg drm_fb_helper_unprepare(fb_helper); 344f005ef32Sjsg kfree(fb_helper); 345f005ef32Sjsg } 346f005ef32Sjsg } 347f005ef32Sjsg 348f005ef32Sjsg #ifdef __sparc64__ 349f005ef32Sjsg void radeondrm_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 350f005ef32Sjsg #endif 351f005ef32Sjsg 352f005ef32Sjsg void radeondrm_burner_cb(void *); 353f005ef32Sjsg 354f005ef32Sjsg static int radeon_fbdev_client_restore(struct drm_client_dev *client) 355f005ef32Sjsg { 356f005ef32Sjsg #ifdef __sparc64__ 357f005ef32Sjsg struct radeon_device *rdev = client->dev->dev_private; 358f005ef32Sjsg fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); 359f005ef32Sjsg #endif 360f005ef32Sjsg drm_fb_helper_lastclose(client->dev); 361f005ef32Sjsg vga_switcheroo_process_delayed_switch(); 362f005ef32Sjsg 363f005ef32Sjsg return 0; 364f005ef32Sjsg } 365f005ef32Sjsg 366f005ef32Sjsg static int radeon_fbdev_client_hotplug(struct drm_client_dev *client) 367f005ef32Sjsg { 368f005ef32Sjsg struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); 369f005ef32Sjsg struct drm_device *dev = client->dev; 370f005ef32Sjsg struct radeon_device *rdev = dev->dev_private; 371f005ef32Sjsg int ret; 372f005ef32Sjsg 373f005ef32Sjsg if (dev->fb_helper) 374f005ef32Sjsg return drm_fb_helper_hotplug_event(dev->fb_helper); 375f005ef32Sjsg 376f005ef32Sjsg ret = drm_fb_helper_init(dev, fb_helper); 377f005ef32Sjsg if (ret) 378f005ef32Sjsg goto err_drm_err; 379f005ef32Sjsg 380f005ef32Sjsg task_set(&rdev->burner_task, radeondrm_burner_cb, rdev); 381f005ef32Sjsg 382f005ef32Sjsg #ifdef __sparc64__ 383f005ef32Sjsg { 384f005ef32Sjsg struct drm_connector_list_iter conn_iter; 385f005ef32Sjsg struct drm_connector *connector; 386f005ef32Sjsg struct drm_cmdline_mode *mode; 387f005ef32Sjsg 388f005ef32Sjsg drm_connector_list_iter_begin(fb_helper->dev, &conn_iter); 389f005ef32Sjsg drm_client_for_each_connector_iter(connector, &conn_iter) { 390f005ef32Sjsg mode = &connector->cmdline_mode; 391f005ef32Sjsg 392f005ef32Sjsg mode->specified = true; 393f005ef32Sjsg mode->xres = rdev->sf.sf_width; 394f005ef32Sjsg mode->yres = rdev->sf.sf_height; 395f005ef32Sjsg mode->bpp_specified = true; 396f005ef32Sjsg mode->bpp = rdev->sf.sf_depth; 397f005ef32Sjsg } 398f005ef32Sjsg drm_connector_list_iter_end(&conn_iter); 399f005ef32Sjsg } 400f005ef32Sjsg #endif 401f005ef32Sjsg 402f005ef32Sjsg if (!drm_drv_uses_atomic_modeset(dev)) 403f005ef32Sjsg drm_helper_disable_unused_functions(dev); 404f005ef32Sjsg 405f005ef32Sjsg ret = drm_fb_helper_initial_config(fb_helper); 406f005ef32Sjsg if (ret) 407f005ef32Sjsg goto err_drm_fb_helper_fini; 408f005ef32Sjsg 409f005ef32Sjsg vga_switcheroo_client_fb_set(rdev->pdev, fb_helper->info); 410f005ef32Sjsg 411f005ef32Sjsg return 0; 412f005ef32Sjsg 413f005ef32Sjsg err_drm_fb_helper_fini: 414f005ef32Sjsg drm_fb_helper_fini(fb_helper); 415f005ef32Sjsg err_drm_err: 416f005ef32Sjsg drm_err(dev, "Failed to setup radeon fbdev emulation (ret=%d)\n", ret); 417f005ef32Sjsg return ret; 418f005ef32Sjsg } 419f005ef32Sjsg 420f005ef32Sjsg static const struct drm_client_funcs radeon_fbdev_client_funcs = { 421f005ef32Sjsg .owner = THIS_MODULE, 422f005ef32Sjsg .unregister = radeon_fbdev_client_unregister, 423f005ef32Sjsg .restore = radeon_fbdev_client_restore, 424f005ef32Sjsg .hotplug = radeon_fbdev_client_hotplug, 425f005ef32Sjsg }; 426f005ef32Sjsg 427f005ef32Sjsg void radeon_fbdev_setup(struct radeon_device *rdev) 428f005ef32Sjsg { 429f005ef32Sjsg struct drm_fb_helper *fb_helper; 430f005ef32Sjsg int bpp_sel = 32; 431f005ef32Sjsg int ret; 432f005ef32Sjsg 433f005ef32Sjsg if (rdev->mc.real_vram_size <= (8 * 1024 * 1024)) 434f005ef32Sjsg bpp_sel = 8; 435f005ef32Sjsg else if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32 * 1024 * 1024)) 436f005ef32Sjsg bpp_sel = 16; 437f005ef32Sjsg 438f005ef32Sjsg fb_helper = kzalloc(sizeof(*fb_helper), GFP_KERNEL); 439f005ef32Sjsg if (!fb_helper) 440f005ef32Sjsg return; 441*33a3edb1Sjsg drm_fb_helper_prepare(rdev_to_drm(rdev), fb_helper, bpp_sel, &radeon_fbdev_fb_helper_funcs); 442f005ef32Sjsg 443*33a3edb1Sjsg ret = drm_client_init(rdev_to_drm(rdev), &fb_helper->client, "radeon-fbdev", 444f005ef32Sjsg &radeon_fbdev_client_funcs); 445f005ef32Sjsg if (ret) { 446*33a3edb1Sjsg drm_err(rdev_to_drm(rdev), "Failed to register client: %d\n", ret); 447f005ef32Sjsg goto err_drm_client_init; 448f005ef32Sjsg } 449f005ef32Sjsg 450f005ef32Sjsg drm_client_register(&fb_helper->client); 451f005ef32Sjsg 452f005ef32Sjsg return; 453f005ef32Sjsg 454f005ef32Sjsg err_drm_client_init: 455f005ef32Sjsg drm_fb_helper_unprepare(fb_helper); 456f005ef32Sjsg kfree(fb_helper); 457f005ef32Sjsg } 458f005ef32Sjsg 459f005ef32Sjsg void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state) 460f005ef32Sjsg { 461*33a3edb1Sjsg if (rdev_to_drm(rdev)->fb_helper) 462*33a3edb1Sjsg drm_fb_helper_set_suspend(rdev_to_drm(rdev)->fb_helper, state); 463f005ef32Sjsg } 464f005ef32Sjsg 465f005ef32Sjsg bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj) 466f005ef32Sjsg { 467*33a3edb1Sjsg struct drm_fb_helper *fb_helper = rdev_to_drm(rdev)->fb_helper; 468f005ef32Sjsg struct drm_gem_object *gobj; 469f005ef32Sjsg 470f005ef32Sjsg if (!fb_helper) 471f005ef32Sjsg return false; 472f005ef32Sjsg 473f005ef32Sjsg gobj = drm_gem_fb_get_obj(fb_helper->fb, 0); 474f005ef32Sjsg if (!gobj) 475f005ef32Sjsg return false; 476f005ef32Sjsg if (gobj != &robj->tbo.base) 477f005ef32Sjsg return false; 478f005ef32Sjsg 479f005ef32Sjsg return true; 480f005ef32Sjsg } 481f005ef32Sjsg 482f005ef32Sjsg void 483f005ef32Sjsg radeondrm_burner(void *v, u_int on, u_int flags) 484f005ef32Sjsg { 485f005ef32Sjsg struct rasops_info *ri = v; 486f005ef32Sjsg struct radeon_device *rdev = ri->ri_hw; 487f005ef32Sjsg 488f005ef32Sjsg task_del(systq, &rdev->burner_task); 489f005ef32Sjsg 490f005ef32Sjsg if (on) 491f005ef32Sjsg rdev->burner_fblank = FB_BLANK_UNBLANK; 492f005ef32Sjsg else { 493f005ef32Sjsg if (flags & WSDISPLAY_BURN_VBLANK) 494f005ef32Sjsg rdev->burner_fblank = FB_BLANK_VSYNC_SUSPEND; 495f005ef32Sjsg else 496f005ef32Sjsg rdev->burner_fblank = FB_BLANK_NORMAL; 497f005ef32Sjsg } 498f005ef32Sjsg 499f005ef32Sjsg /* 500f005ef32Sjsg * Setting the DPMS mode may sleep while waiting for vblank so 501f005ef32Sjsg * hand things off to a taskq. 502f005ef32Sjsg */ 503f005ef32Sjsg task_add(systq, &rdev->burner_task); 504f005ef32Sjsg } 505f005ef32Sjsg 506f005ef32Sjsg void 507f005ef32Sjsg radeondrm_burner_cb(void *arg1) 508f005ef32Sjsg { 509f005ef32Sjsg struct radeon_device *rdev = arg1; 510f005ef32Sjsg struct drm_fb_helper *helper = rdev->ddev->fb_helper; 511f005ef32Sjsg 512f005ef32Sjsg drm_fb_helper_blank(rdev->burner_fblank, helper->info); 513f005ef32Sjsg } 514