1*7ccd5a2cSjsg /* 2*7ccd5a2cSjsg * Copyright 2011 Advanced Micro Devices, Inc. 3*7ccd5a2cSjsg * 4*7ccd5a2cSjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*7ccd5a2cSjsg * copy of this software and associated documentation files (the "Software"), 6*7ccd5a2cSjsg * to deal in the Software without restriction, including without limitation 7*7ccd5a2cSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*7ccd5a2cSjsg * and/or sell copies of the Software, and to permit persons to whom the 9*7ccd5a2cSjsg * Software is furnished to do so, subject to the following conditions: 10*7ccd5a2cSjsg * 11*7ccd5a2cSjsg * The above copyright notice and this permission notice shall be included in 12*7ccd5a2cSjsg * all copies or substantial portions of the Software. 13*7ccd5a2cSjsg * 14*7ccd5a2cSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*7ccd5a2cSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*7ccd5a2cSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*7ccd5a2cSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*7ccd5a2cSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*7ccd5a2cSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*7ccd5a2cSjsg * OTHER DEALINGS IN THE SOFTWARE. 21*7ccd5a2cSjsg * 22*7ccd5a2cSjsg */ 23*7ccd5a2cSjsg #ifndef __CYPRESS_DPM_H__ 24*7ccd5a2cSjsg #define __CYPRESS_DPM_H__ 25*7ccd5a2cSjsg 26*7ccd5a2cSjsg #include "rv770_dpm.h" 27*7ccd5a2cSjsg #include "evergreen_smc.h" 28*7ccd5a2cSjsg 29*7ccd5a2cSjsg struct evergreen_mc_reg_entry { 30*7ccd5a2cSjsg u32 mclk_max; 31*7ccd5a2cSjsg u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 32*7ccd5a2cSjsg }; 33*7ccd5a2cSjsg 34*7ccd5a2cSjsg struct evergreen_mc_reg_table { 35*7ccd5a2cSjsg u8 last; 36*7ccd5a2cSjsg u8 num_entries; 37*7ccd5a2cSjsg u16 valid_flag; 38*7ccd5a2cSjsg struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 39*7ccd5a2cSjsg SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 40*7ccd5a2cSjsg }; 41*7ccd5a2cSjsg 42*7ccd5a2cSjsg struct evergreen_ulv_param { 43*7ccd5a2cSjsg bool supported; 44*7ccd5a2cSjsg struct rv7xx_pl *pl; 45*7ccd5a2cSjsg }; 46*7ccd5a2cSjsg 47*7ccd5a2cSjsg struct evergreen_arb_registers { 48*7ccd5a2cSjsg u32 mc_arb_dram_timing; 49*7ccd5a2cSjsg u32 mc_arb_dram_timing2; 50*7ccd5a2cSjsg u32 mc_arb_rfsh_rate; 51*7ccd5a2cSjsg u32 mc_arb_burst_time; 52*7ccd5a2cSjsg }; 53*7ccd5a2cSjsg 54*7ccd5a2cSjsg struct at { 55*7ccd5a2cSjsg u32 rlp; 56*7ccd5a2cSjsg u32 rmp; 57*7ccd5a2cSjsg u32 lhp; 58*7ccd5a2cSjsg u32 lmp; 59*7ccd5a2cSjsg }; 60*7ccd5a2cSjsg 61*7ccd5a2cSjsg struct evergreen_power_info { 62*7ccd5a2cSjsg /* must be first! */ 63*7ccd5a2cSjsg struct rv7xx_power_info rv7xx; 64*7ccd5a2cSjsg /* flags */ 65*7ccd5a2cSjsg bool vddci_control; 66*7ccd5a2cSjsg bool dynamic_ac_timing; 67*7ccd5a2cSjsg bool abm; 68*7ccd5a2cSjsg bool mcls; 69*7ccd5a2cSjsg bool light_sleep; 70*7ccd5a2cSjsg bool memory_transition; 71*7ccd5a2cSjsg bool pcie_performance_request; 72*7ccd5a2cSjsg bool pcie_performance_request_registered; 73*7ccd5a2cSjsg bool sclk_deep_sleep; 74*7ccd5a2cSjsg bool dll_default_on; 75*7ccd5a2cSjsg bool ls_clock_gating; 76*7ccd5a2cSjsg bool smu_uvd_hs; 77*7ccd5a2cSjsg bool uvd_enabled; 78*7ccd5a2cSjsg /* stored values */ 79*7ccd5a2cSjsg u16 acpi_vddci; 80*7ccd5a2cSjsg u8 mvdd_high_index; 81*7ccd5a2cSjsg u8 mvdd_low_index; 82*7ccd5a2cSjsg u32 mclk_edc_wr_enable_threshold; 83*7ccd5a2cSjsg struct evergreen_mc_reg_table mc_reg_table; 84*7ccd5a2cSjsg struct atom_voltage_table vddc_voltage_table; 85*7ccd5a2cSjsg struct atom_voltage_table vddci_voltage_table; 86*7ccd5a2cSjsg struct evergreen_arb_registers bootup_arb_registers; 87*7ccd5a2cSjsg struct evergreen_ulv_param ulv; 88*7ccd5a2cSjsg struct at ats[2]; 89*7ccd5a2cSjsg /* smc offsets */ 90*7ccd5a2cSjsg u16 mc_reg_table_start; 91*7ccd5a2cSjsg struct radeon_ps current_rps; 92*7ccd5a2cSjsg struct rv7xx_ps current_ps; 93*7ccd5a2cSjsg struct radeon_ps requested_rps; 94*7ccd5a2cSjsg struct rv7xx_ps requested_ps; 95*7ccd5a2cSjsg }; 96*7ccd5a2cSjsg 97*7ccd5a2cSjsg #define CYPRESS_HASI_DFLT 400000 98*7ccd5a2cSjsg #define CYPRESS_MGCGTTLOCAL0_DFLT 0x00000000 99*7ccd5a2cSjsg #define CYPRESS_MGCGTTLOCAL1_DFLT 0x00000000 100*7ccd5a2cSjsg #define CYPRESS_MGCGTTLOCAL2_DFLT 0x00000000 101*7ccd5a2cSjsg #define CYPRESS_MGCGTTLOCAL3_DFLT 0x00000000 102*7ccd5a2cSjsg #define CYPRESS_MGCGCGTSSMCTRL_DFLT 0x81944bc0 103*7ccd5a2cSjsg #define REDWOOD_MGCGCGTSSMCTRL_DFLT 0x6e944040 104*7ccd5a2cSjsg #define CEDAR_MGCGCGTSSMCTRL_DFLT 0x46944040 105*7ccd5a2cSjsg #define CYPRESS_VRC_DFLT 0xC00033 106*7ccd5a2cSjsg 107*7ccd5a2cSjsg #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 108*7ccd5a2cSjsg #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 109*7ccd5a2cSjsg #define PCIE_PERF_REQ_PECI_GEN1 2 110*7ccd5a2cSjsg #define PCIE_PERF_REQ_PECI_GEN2 3 111*7ccd5a2cSjsg #define PCIE_PERF_REQ_PECI_GEN3 4 112*7ccd5a2cSjsg 113*7ccd5a2cSjsg int cypress_convert_power_level_to_smc(struct radeon_device *rdev, 114*7ccd5a2cSjsg struct rv7xx_pl *pl, 115*7ccd5a2cSjsg RV770_SMC_HW_PERFORMANCE_LEVEL *level, 116*7ccd5a2cSjsg u8 watermark_level); 117*7ccd5a2cSjsg int cypress_populate_smc_acpi_state(struct radeon_device *rdev, 118*7ccd5a2cSjsg RV770_SMC_STATETABLE *table); 119*7ccd5a2cSjsg int cypress_populate_smc_voltage_tables(struct radeon_device *rdev, 120*7ccd5a2cSjsg RV770_SMC_STATETABLE *table); 121*7ccd5a2cSjsg int cypress_populate_smc_initial_state(struct radeon_device *rdev, 122*7ccd5a2cSjsg struct radeon_ps *radeon_initial_state, 123*7ccd5a2cSjsg RV770_SMC_STATETABLE *table); 124*7ccd5a2cSjsg u32 cypress_calculate_burst_time(struct radeon_device *rdev, 125*7ccd5a2cSjsg u32 engine_clock, u32 memory_clock); 126*7ccd5a2cSjsg void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev, 127*7ccd5a2cSjsg struct radeon_ps *radeon_new_state, 128*7ccd5a2cSjsg struct radeon_ps *radeon_current_state); 129*7ccd5a2cSjsg int cypress_upload_sw_state(struct radeon_device *rdev, 130*7ccd5a2cSjsg struct radeon_ps *radeon_new_state); 131*7ccd5a2cSjsg int cypress_upload_mc_reg_table(struct radeon_device *rdev, 132*7ccd5a2cSjsg struct radeon_ps *radeon_new_state); 133*7ccd5a2cSjsg void cypress_program_memory_timing_parameters(struct radeon_device *rdev, 134*7ccd5a2cSjsg struct radeon_ps *radeon_new_state); 135*7ccd5a2cSjsg void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 136*7ccd5a2cSjsg struct radeon_ps *radeon_new_state, 137*7ccd5a2cSjsg struct radeon_ps *radeon_current_state); 138*7ccd5a2cSjsg int cypress_construct_voltage_tables(struct radeon_device *rdev); 139*7ccd5a2cSjsg int cypress_get_mvdd_configuration(struct radeon_device *rdev); 140*7ccd5a2cSjsg void cypress_enable_spread_spectrum(struct radeon_device *rdev, 141*7ccd5a2cSjsg bool enable); 142*7ccd5a2cSjsg void cypress_enable_display_gap(struct radeon_device *rdev); 143*7ccd5a2cSjsg int cypress_get_table_locations(struct radeon_device *rdev); 144*7ccd5a2cSjsg int cypress_populate_mc_reg_table(struct radeon_device *rdev, 145*7ccd5a2cSjsg struct radeon_ps *radeon_boot_state); 146*7ccd5a2cSjsg void cypress_program_response_times(struct radeon_device *rdev); 147*7ccd5a2cSjsg int cypress_notify_smc_display_change(struct radeon_device *rdev, 148*7ccd5a2cSjsg bool has_display); 149*7ccd5a2cSjsg void cypress_enable_sclk_control(struct radeon_device *rdev, 150*7ccd5a2cSjsg bool enable); 151*7ccd5a2cSjsg void cypress_enable_mclk_control(struct radeon_device *rdev, 152*7ccd5a2cSjsg bool enable); 153*7ccd5a2cSjsg void cypress_start_dpm(struct radeon_device *rdev); 154*7ccd5a2cSjsg void cypress_advertise_gen2_capability(struct radeon_device *rdev); 155*7ccd5a2cSjsg u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf); 156*7ccd5a2cSjsg u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev, 157*7ccd5a2cSjsg u32 memory_clock, bool strobe_mode); 158*7ccd5a2cSjsg u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk); 159*7ccd5a2cSjsg 160*7ccd5a2cSjsg #endif 161