1c349dbc7Sjsg /* 2c349dbc7Sjsg * SPDX-License-Identifier: MIT 3c349dbc7Sjsg * 4c349dbc7Sjsg * Copyright © 2019 Intel Corporation 5c349dbc7Sjsg */ 6c349dbc7Sjsg 7c349dbc7Sjsg #ifndef IGT_LIVE_TEST_H 8c349dbc7Sjsg #define IGT_LIVE_TEST_H 9c349dbc7Sjsg 10*f005ef32Sjsg #include "gt/intel_gt_defines.h" /* for I915_MAX_GT */ 11c349dbc7Sjsg #include "gt/intel_engine.h" /* for I915_NUM_ENGINES */ 12c349dbc7Sjsg 13c349dbc7Sjsg struct drm_i915_private; 14c349dbc7Sjsg 15c349dbc7Sjsg struct igt_live_test { 16c349dbc7Sjsg struct drm_i915_private *i915; 17c349dbc7Sjsg const char *func; 18c349dbc7Sjsg const char *name; 19c349dbc7Sjsg 20c349dbc7Sjsg unsigned int reset_global; 21*f005ef32Sjsg unsigned int reset_engine[I915_MAX_GT][I915_NUM_ENGINES]; 22c349dbc7Sjsg }; 23c349dbc7Sjsg 24c349dbc7Sjsg /* 25c349dbc7Sjsg * Flush the GPU state before and after the test to ensure that no residual 26c349dbc7Sjsg * code is running on the GPU that may affect this test. Also compare the 27c349dbc7Sjsg * state before and after the test and alert if it unexpectedly changes, 28c349dbc7Sjsg * e.g. if the GPU was reset. 29c349dbc7Sjsg */ 30c349dbc7Sjsg int igt_live_test_begin(struct igt_live_test *t, 31c349dbc7Sjsg struct drm_i915_private *i915, 32c349dbc7Sjsg const char *func, 33c349dbc7Sjsg const char *name); 34c349dbc7Sjsg int igt_live_test_end(struct igt_live_test *t); 35c349dbc7Sjsg 36c349dbc7Sjsg #endif /* IGT_LIVE_TEST_H */ 37