15ca02815Sjsg // SPDX-License-Identifier: MIT
2c349dbc7Sjsg /*
3c349dbc7Sjsg * Copyright © 2019 Intel Corporation
4c349dbc7Sjsg */
5c349dbc7Sjsg
6c349dbc7Sjsg #include "selftest_llc.h"
7c349dbc7Sjsg #include "intel_rps.h"
8c349dbc7Sjsg
gen6_verify_ring_freq(struct intel_llc * llc)9c349dbc7Sjsg static int gen6_verify_ring_freq(struct intel_llc *llc)
10c349dbc7Sjsg {
11c349dbc7Sjsg struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
12c349dbc7Sjsg struct ia_constants consts;
13c349dbc7Sjsg intel_wakeref_t wakeref;
14c349dbc7Sjsg unsigned int gpu_freq;
15c349dbc7Sjsg int err = 0;
16c349dbc7Sjsg
17c349dbc7Sjsg wakeref = intel_runtime_pm_get(llc_to_gt(llc)->uncore->rpm);
18c349dbc7Sjsg
19c349dbc7Sjsg if (!get_ia_constants(llc, &consts))
20c349dbc7Sjsg goto out_rpm;
21c349dbc7Sjsg
22c349dbc7Sjsg for (gpu_freq = consts.min_gpu_freq;
23c349dbc7Sjsg gpu_freq <= consts.max_gpu_freq;
24c349dbc7Sjsg gpu_freq++) {
25c349dbc7Sjsg struct intel_rps *rps = &llc_to_gt(llc)->rps;
26c349dbc7Sjsg
27c349dbc7Sjsg unsigned int ia_freq, ring_freq, found;
28c349dbc7Sjsg u32 val;
29c349dbc7Sjsg
30c349dbc7Sjsg calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
31c349dbc7Sjsg
32c349dbc7Sjsg val = gpu_freq;
33*1bb76ff1Sjsg if (snb_pcode_read(llc_to_gt(llc)->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
34c349dbc7Sjsg &val, NULL)) {
35c349dbc7Sjsg pr_err("Failed to read freq table[%d], range [%d, %d]\n",
36c349dbc7Sjsg gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
37c349dbc7Sjsg err = -ENXIO;
38c349dbc7Sjsg break;
39c349dbc7Sjsg }
40c349dbc7Sjsg
41c349dbc7Sjsg found = (val >> 0) & 0xff;
42c349dbc7Sjsg if (found != ia_freq) {
43c349dbc7Sjsg pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
44c349dbc7Sjsg gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
455ca02815Sjsg intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
46c349dbc7Sjsg found, ia_freq);
47c349dbc7Sjsg err = -EINVAL;
48c349dbc7Sjsg break;
49c349dbc7Sjsg }
50c349dbc7Sjsg
51c349dbc7Sjsg found = (val >> 8) & 0xff;
52c349dbc7Sjsg if (found != ring_freq) {
53c349dbc7Sjsg pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
54c349dbc7Sjsg gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
555ca02815Sjsg intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
56c349dbc7Sjsg found, ring_freq);
57c349dbc7Sjsg err = -EINVAL;
58c349dbc7Sjsg break;
59c349dbc7Sjsg }
60c349dbc7Sjsg }
61c349dbc7Sjsg
62c349dbc7Sjsg out_rpm:
63c349dbc7Sjsg intel_runtime_pm_put(llc_to_gt(llc)->uncore->rpm, wakeref);
64c349dbc7Sjsg return err;
65c349dbc7Sjsg }
66c349dbc7Sjsg
st_llc_verify(struct intel_llc * llc)67c349dbc7Sjsg int st_llc_verify(struct intel_llc *llc)
68c349dbc7Sjsg {
69c349dbc7Sjsg return gen6_verify_ring_freq(llc);
70c349dbc7Sjsg }
71