11bb76ff1Sjsg // SPDX-License-Identifier: MIT 21bb76ff1Sjsg /* 31bb76ff1Sjsg * Copyright © 2021 Intel Corporation 41bb76ff1Sjsg */ 51bb76ff1Sjsg 61bb76ff1Sjsg #include <drm/drm_managed.h> 71bb76ff1Sjsg 81bb76ff1Sjsg #include "i915_drv.h" 91bb76ff1Sjsg #include "gt/intel_gt.h" 101bb76ff1Sjsg #include "gt/intel_sa_media.h" 111bb76ff1Sjsg intel_sa_mediagt_setup(struct intel_gt * gt,phys_addr_t phys_addr,u32 gsi_offset)121bb76ff1Sjsgint intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr, 131bb76ff1Sjsg u32 gsi_offset) 141bb76ff1Sjsg { 151bb76ff1Sjsg struct drm_i915_private *i915 = gt->i915; 161bb76ff1Sjsg struct intel_uncore *uncore; 171bb76ff1Sjsg 181bb76ff1Sjsg uncore = drmm_kzalloc(&i915->drm, sizeof(*uncore), GFP_KERNEL); 191bb76ff1Sjsg if (!uncore) 201bb76ff1Sjsg return -ENOMEM; 211bb76ff1Sjsg 221bb76ff1Sjsg uncore->gsi_offset = gsi_offset; 231bb76ff1Sjsg 241bb76ff1Sjsg gt->irq_lock = to_gt(i915)->irq_lock; 251bb76ff1Sjsg intel_gt_common_init_early(gt); 261bb76ff1Sjsg intel_uncore_init_early(uncore, gt); 271bb76ff1Sjsg 281bb76ff1Sjsg /* 291bb76ff1Sjsg * Standalone media shares the general MMIO space with the primary 301bb76ff1Sjsg * GT. We'll re-use the primary GT's mapping. 311bb76ff1Sjsg */ 32*f005ef32Sjsg uncore->regs = intel_uncore_regs(&i915->uncore); 331bb76ff1Sjsg if (drm_WARN_ON(&i915->drm, uncore->regs == NULL)) 341bb76ff1Sjsg return -EIO; 351bb76ff1Sjsg 361bb76ff1Sjsg gt->uncore = uncore; 371bb76ff1Sjsg gt->phys_addr = phys_addr; 381bb76ff1Sjsg 391bb76ff1Sjsg /* 401bb76ff1Sjsg * For current platforms we can assume there's only a single 411bb76ff1Sjsg * media GT and cache it for quick lookup. 421bb76ff1Sjsg */ 431bb76ff1Sjsg drm_WARN_ON(&i915->drm, i915->media_gt); 441bb76ff1Sjsg i915->media_gt = gt; 451bb76ff1Sjsg 461bb76ff1Sjsg return 0; 471bb76ff1Sjsg } 48