11bb76ff1Sjsg /* SPDX-License-Identifier: MIT */ 21bb76ff1Sjsg /* 31bb76ff1Sjsg * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. 41bb76ff1Sjsg */ 51bb76ff1Sjsg #ifndef __INTEL_GSC_DEV_H__ 61bb76ff1Sjsg #define __INTEL_GSC_DEV_H__ 71bb76ff1Sjsg 81bb76ff1Sjsg #include <linux/types.h> 91bb76ff1Sjsg 101bb76ff1Sjsg struct drm_i915_private; 111bb76ff1Sjsg struct intel_gt; 121bb76ff1Sjsg struct mei_aux_device; 131bb76ff1Sjsg 141bb76ff1Sjsg #define INTEL_GSC_NUM_INTERFACES 2 151bb76ff1Sjsg /* 161bb76ff1Sjsg * The HECI1 bit corresponds to bit15 and HECI2 to bit14. 171bb76ff1Sjsg * The reason for this is to allow growth for more interfaces in the future. 181bb76ff1Sjsg */ 191bb76ff1Sjsg #define GSC_IRQ_INTF(_x) BIT(15 - (_x)) 201bb76ff1Sjsg 211bb76ff1Sjsg /** 221bb76ff1Sjsg * struct intel_gsc - graphics security controller 231bb76ff1Sjsg * 241bb76ff1Sjsg * @gem_obj: scratch memory GSC operations 251bb76ff1Sjsg * @intf : gsc interface 261bb76ff1Sjsg */ 271bb76ff1Sjsg struct intel_gsc { 281bb76ff1Sjsg struct intel_gsc_intf { 291bb76ff1Sjsg struct mei_aux_device *adev; 301bb76ff1Sjsg struct drm_i915_gem_object *gem_obj; 311bb76ff1Sjsg int irq; 321bb76ff1Sjsg unsigned int id; 331bb76ff1Sjsg } intf[INTEL_GSC_NUM_INTERFACES]; 341bb76ff1Sjsg }; 351bb76ff1Sjsg 36*f005ef32Sjsg void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915); 371bb76ff1Sjsg void intel_gsc_fini(struct intel_gsc *gsc); 381bb76ff1Sjsg void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir); 391bb76ff1Sjsg 401bb76ff1Sjsg #endif /* __INTEL_GSC_DEV_H__ */ 41