xref: /openbsd-src/sys/dev/pci/drm/i915/display/intel_dvo.c (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1c349dbc7Sjsg /*
2c349dbc7Sjsg  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3c349dbc7Sjsg  * Copyright © 2006-2007 Intel Corporation
4c349dbc7Sjsg  *
5c349dbc7Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
6c349dbc7Sjsg  * copy of this software and associated documentation files (the "Software"),
7c349dbc7Sjsg  * to deal in the Software without restriction, including without limitation
8c349dbc7Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9c349dbc7Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
10c349dbc7Sjsg  * Software is furnished to do so, subject to the following conditions:
11c349dbc7Sjsg  *
12c349dbc7Sjsg  * The above copyright notice and this permission notice (including the next
13c349dbc7Sjsg  * paragraph) shall be included in all copies or substantial portions of the
14c349dbc7Sjsg  * Software.
15c349dbc7Sjsg  *
16c349dbc7Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17c349dbc7Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18c349dbc7Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19c349dbc7Sjsg  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20c349dbc7Sjsg  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21c349dbc7Sjsg  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22c349dbc7Sjsg  * DEALINGS IN THE SOFTWARE.
23c349dbc7Sjsg  *
24c349dbc7Sjsg  * Authors:
25c349dbc7Sjsg  *	Eric Anholt <eric@anholt.net>
26c349dbc7Sjsg  */
27c349dbc7Sjsg 
28c349dbc7Sjsg #include <linux/i2c.h>
29c349dbc7Sjsg #include <linux/slab.h>
30c349dbc7Sjsg 
31c349dbc7Sjsg #include <drm/drm_atomic_helper.h>
32c349dbc7Sjsg #include <drm/drm_crtc.h>
33c349dbc7Sjsg 
34c349dbc7Sjsg #include "i915_drv.h"
35*f005ef32Sjsg #include "i915_reg.h"
36c349dbc7Sjsg #include "intel_connector.h"
375ca02815Sjsg #include "intel_de.h"
38c349dbc7Sjsg #include "intel_display_types.h"
39c349dbc7Sjsg #include "intel_dvo.h"
40c349dbc7Sjsg #include "intel_dvo_dev.h"
41*f005ef32Sjsg #include "intel_dvo_regs.h"
42c349dbc7Sjsg #include "intel_gmbus.h"
43c349dbc7Sjsg #include "intel_panel.h"
44c349dbc7Sjsg 
45c349dbc7Sjsg #define INTEL_DVO_CHIP_NONE	0
46c349dbc7Sjsg #define INTEL_DVO_CHIP_LVDS	1
47c349dbc7Sjsg #define INTEL_DVO_CHIP_TMDS	2
48c349dbc7Sjsg #define INTEL_DVO_CHIP_TVOUT	4
49c349dbc7Sjsg #define INTEL_DVO_CHIP_LVDS_NO_FIXED	5
50c349dbc7Sjsg 
51c349dbc7Sjsg #define SIL164_ADDR	0x38
52c349dbc7Sjsg #define CH7xxx_ADDR	0x76
53c349dbc7Sjsg #define TFP410_ADDR	0x38
54c349dbc7Sjsg #define NS2501_ADDR     0x38
55c349dbc7Sjsg 
56c349dbc7Sjsg static const struct intel_dvo_device intel_dvo_devices[] = {
57c349dbc7Sjsg 	{
58c349dbc7Sjsg 		.type = INTEL_DVO_CHIP_TMDS,
59c349dbc7Sjsg 		.name = "sil164",
60*f005ef32Sjsg 		.port = PORT_C,
61c349dbc7Sjsg 		.slave_addr = SIL164_ADDR,
62c349dbc7Sjsg 		.dev_ops = &sil164_ops,
63c349dbc7Sjsg 	},
64c349dbc7Sjsg 	{
65c349dbc7Sjsg 		.type = INTEL_DVO_CHIP_TMDS,
66c349dbc7Sjsg 		.name = "ch7xxx",
67*f005ef32Sjsg 		.port = PORT_C,
68c349dbc7Sjsg 		.slave_addr = CH7xxx_ADDR,
69c349dbc7Sjsg 		.dev_ops = &ch7xxx_ops,
70c349dbc7Sjsg 	},
71c349dbc7Sjsg 	{
72c349dbc7Sjsg 		.type = INTEL_DVO_CHIP_TMDS,
73c349dbc7Sjsg 		.name = "ch7xxx",
74*f005ef32Sjsg 		.port = PORT_C,
75c349dbc7Sjsg 		.slave_addr = 0x75, /* For some ch7010 */
76c349dbc7Sjsg 		.dev_ops = &ch7xxx_ops,
77c349dbc7Sjsg 	},
78c349dbc7Sjsg 	{
79c349dbc7Sjsg 		.type = INTEL_DVO_CHIP_LVDS,
80c349dbc7Sjsg 		.name = "ivch",
81*f005ef32Sjsg 		.port = PORT_A,
82c349dbc7Sjsg 		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
83c349dbc7Sjsg 		.dev_ops = &ivch_ops,
84c349dbc7Sjsg 	},
85c349dbc7Sjsg 	{
86c349dbc7Sjsg 		.type = INTEL_DVO_CHIP_TMDS,
87c349dbc7Sjsg 		.name = "tfp410",
88*f005ef32Sjsg 		.port = PORT_C,
89c349dbc7Sjsg 		.slave_addr = TFP410_ADDR,
90c349dbc7Sjsg 		.dev_ops = &tfp410_ops,
91c349dbc7Sjsg 	},
92c349dbc7Sjsg 	{
93c349dbc7Sjsg 		.type = INTEL_DVO_CHIP_LVDS,
94c349dbc7Sjsg 		.name = "ch7017",
95*f005ef32Sjsg 		.port = PORT_C,
96c349dbc7Sjsg 		.slave_addr = 0x75,
97c349dbc7Sjsg 		.gpio = GMBUS_PIN_DPB,
98c349dbc7Sjsg 		.dev_ops = &ch7017_ops,
99c349dbc7Sjsg 	},
100c349dbc7Sjsg 	{
101c349dbc7Sjsg 		.type = INTEL_DVO_CHIP_LVDS_NO_FIXED,
102c349dbc7Sjsg 		.name = "ns2501",
103*f005ef32Sjsg 		.port = PORT_B,
104c349dbc7Sjsg 		.slave_addr = NS2501_ADDR,
105c349dbc7Sjsg 		.dev_ops = &ns2501_ops,
106c349dbc7Sjsg 	},
107c349dbc7Sjsg };
108c349dbc7Sjsg 
109c349dbc7Sjsg struct intel_dvo {
110c349dbc7Sjsg 	struct intel_encoder base;
111c349dbc7Sjsg 
112c349dbc7Sjsg 	struct intel_dvo_device dev;
113c349dbc7Sjsg 
114c349dbc7Sjsg 	struct intel_connector *attached_connector;
115c349dbc7Sjsg };
116c349dbc7Sjsg 
enc_to_dvo(struct intel_encoder * encoder)117c349dbc7Sjsg static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
118c349dbc7Sjsg {
119c349dbc7Sjsg 	return container_of(encoder, struct intel_dvo, base);
120c349dbc7Sjsg }
121c349dbc7Sjsg 
intel_attached_dvo(struct intel_connector * connector)122c349dbc7Sjsg static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector)
123c349dbc7Sjsg {
124c349dbc7Sjsg 	return enc_to_dvo(intel_attached_encoder(connector));
125c349dbc7Sjsg }
126c349dbc7Sjsg 
intel_dvo_connector_get_hw_state(struct intel_connector * connector)127c349dbc7Sjsg static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
128c349dbc7Sjsg {
129*f005ef32Sjsg 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
130*f005ef32Sjsg 	struct intel_encoder *encoder = intel_attached_encoder(connector);
131*f005ef32Sjsg 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
132*f005ef32Sjsg 	enum port port = encoder->port;
133c349dbc7Sjsg 	u32 tmp;
134c349dbc7Sjsg 
135*f005ef32Sjsg 	tmp = intel_de_read(i915, DVO(port));
136c349dbc7Sjsg 
137c349dbc7Sjsg 	if (!(tmp & DVO_ENABLE))
138c349dbc7Sjsg 		return false;
139c349dbc7Sjsg 
140c349dbc7Sjsg 	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
141c349dbc7Sjsg }
142c349dbc7Sjsg 
intel_dvo_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)143c349dbc7Sjsg static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
144c349dbc7Sjsg 				   enum pipe *pipe)
145c349dbc7Sjsg {
146*f005ef32Sjsg 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
147*f005ef32Sjsg 	enum port port = encoder->port;
148c349dbc7Sjsg 	u32 tmp;
149c349dbc7Sjsg 
150*f005ef32Sjsg 	tmp = intel_de_read(i915, DVO(port));
151c349dbc7Sjsg 
152*f005ef32Sjsg 	*pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp);
153c349dbc7Sjsg 
154c349dbc7Sjsg 	return tmp & DVO_ENABLE;
155c349dbc7Sjsg }
156c349dbc7Sjsg 
intel_dvo_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)157c349dbc7Sjsg static void intel_dvo_get_config(struct intel_encoder *encoder,
158c349dbc7Sjsg 				 struct intel_crtc_state *pipe_config)
159c349dbc7Sjsg {
160*f005ef32Sjsg 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
161*f005ef32Sjsg 	enum port port = encoder->port;
162c349dbc7Sjsg 	u32 tmp, flags = 0;
163c349dbc7Sjsg 
164c349dbc7Sjsg 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
165c349dbc7Sjsg 
166*f005ef32Sjsg 	tmp = intel_de_read(i915, DVO(port));
167c349dbc7Sjsg 	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
168c349dbc7Sjsg 		flags |= DRM_MODE_FLAG_PHSYNC;
169c349dbc7Sjsg 	else
170c349dbc7Sjsg 		flags |= DRM_MODE_FLAG_NHSYNC;
171c349dbc7Sjsg 	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
172c349dbc7Sjsg 		flags |= DRM_MODE_FLAG_PVSYNC;
173c349dbc7Sjsg 	else
174c349dbc7Sjsg 		flags |= DRM_MODE_FLAG_NVSYNC;
175c349dbc7Sjsg 
176c349dbc7Sjsg 	pipe_config->hw.adjusted_mode.flags |= flags;
177c349dbc7Sjsg 
178c349dbc7Sjsg 	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
179c349dbc7Sjsg }
180c349dbc7Sjsg 
intel_disable_dvo(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)181ad8b1aafSjsg static void intel_disable_dvo(struct intel_atomic_state *state,
182ad8b1aafSjsg 			      struct intel_encoder *encoder,
183c349dbc7Sjsg 			      const struct intel_crtc_state *old_crtc_state,
184c349dbc7Sjsg 			      const struct drm_connector_state *old_conn_state)
185c349dbc7Sjsg {
186*f005ef32Sjsg 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
187c349dbc7Sjsg 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
188*f005ef32Sjsg 	enum port port = encoder->port;
189c349dbc7Sjsg 
190c349dbc7Sjsg 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
191*f005ef32Sjsg 
192*f005ef32Sjsg 	intel_de_rmw(i915, DVO(port), DVO_ENABLE, 0);
193*f005ef32Sjsg 	intel_de_posting_read(i915, DVO(port));
194c349dbc7Sjsg }
195c349dbc7Sjsg 
intel_enable_dvo(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)196ad8b1aafSjsg static void intel_enable_dvo(struct intel_atomic_state *state,
197ad8b1aafSjsg 			     struct intel_encoder *encoder,
198c349dbc7Sjsg 			     const struct intel_crtc_state *pipe_config,
199c349dbc7Sjsg 			     const struct drm_connector_state *conn_state)
200c349dbc7Sjsg {
201*f005ef32Sjsg 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
202c349dbc7Sjsg 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
203*f005ef32Sjsg 	enum port port = encoder->port;
204c349dbc7Sjsg 
205c349dbc7Sjsg 	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
206c349dbc7Sjsg 					 &pipe_config->hw.mode,
207c349dbc7Sjsg 					 &pipe_config->hw.adjusted_mode);
208c349dbc7Sjsg 
209*f005ef32Sjsg 	intel_de_rmw(i915, DVO(port), 0, DVO_ENABLE);
210*f005ef32Sjsg 	intel_de_posting_read(i915, DVO(port));
211c349dbc7Sjsg 
212c349dbc7Sjsg 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
213c349dbc7Sjsg }
214c349dbc7Sjsg 
215c349dbc7Sjsg static enum drm_mode_status
intel_dvo_mode_valid(struct drm_connector * _connector,struct drm_display_mode * mode)216*f005ef32Sjsg intel_dvo_mode_valid(struct drm_connector *_connector,
217c349dbc7Sjsg 		     struct drm_display_mode *mode)
218c349dbc7Sjsg {
219*f005ef32Sjsg 	struct intel_connector *connector = to_intel_connector(_connector);
220*f005ef32Sjsg 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
221*f005ef32Sjsg 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
222c349dbc7Sjsg 	const struct drm_display_mode *fixed_mode =
223*f005ef32Sjsg 		intel_panel_fixed_mode(connector, mode);
224*f005ef32Sjsg 	int max_dotclk = to_i915(connector->base.dev)->max_dotclk_freq;
225c349dbc7Sjsg 	int target_clock = mode->clock;
2262bd53da4Sjsg 	enum drm_mode_status status;
2272bd53da4Sjsg 
2282bd53da4Sjsg 	status = intel_cpu_transcoder_mode_valid(i915, mode);
2292bd53da4Sjsg 	if (status != MODE_OK)
2302bd53da4Sjsg 		return status;
231c349dbc7Sjsg 
232c349dbc7Sjsg 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
233c349dbc7Sjsg 		return MODE_NO_DBLESCAN;
234c349dbc7Sjsg 
235c349dbc7Sjsg 	/* XXX: Validate clock range */
236c349dbc7Sjsg 
237c349dbc7Sjsg 	if (fixed_mode) {
2381bb76ff1Sjsg 		enum drm_mode_status status;
2391bb76ff1Sjsg 
240*f005ef32Sjsg 		status = intel_panel_mode_valid(connector, mode);
2411bb76ff1Sjsg 		if (status != MODE_OK)
2421bb76ff1Sjsg 			return status;
243c349dbc7Sjsg 
244c349dbc7Sjsg 		target_clock = fixed_mode->clock;
245c349dbc7Sjsg 	}
246c349dbc7Sjsg 
247c349dbc7Sjsg 	if (target_clock > max_dotclk)
248c349dbc7Sjsg 		return MODE_CLOCK_HIGH;
249c349dbc7Sjsg 
250c349dbc7Sjsg 	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
251c349dbc7Sjsg }
252c349dbc7Sjsg 
intel_dvo_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)253c349dbc7Sjsg static int intel_dvo_compute_config(struct intel_encoder *encoder,
254c349dbc7Sjsg 				    struct intel_crtc_state *pipe_config,
255c349dbc7Sjsg 				    struct drm_connector_state *conn_state)
256c349dbc7Sjsg {
257c349dbc7Sjsg 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
2581bb76ff1Sjsg 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
259c349dbc7Sjsg 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2601bb76ff1Sjsg 	const struct drm_display_mode *fixed_mode =
2611bb76ff1Sjsg 		intel_panel_fixed_mode(intel_dvo->attached_connector, adjusted_mode);
262c349dbc7Sjsg 
263c349dbc7Sjsg 	/*
264c349dbc7Sjsg 	 * If we have timings from the BIOS for the panel, put them in
265c349dbc7Sjsg 	 * to the adjusted mode.  The CRTC will be set up for this mode,
266c349dbc7Sjsg 	 * with the panel scaling set up to source from the H/VDisplay
267c349dbc7Sjsg 	 * of the original mode.
268c349dbc7Sjsg 	 */
2691bb76ff1Sjsg 	if (fixed_mode) {
2701bb76ff1Sjsg 		int ret;
2711bb76ff1Sjsg 
2721bb76ff1Sjsg 		ret = intel_panel_compute_config(connector, adjusted_mode);
2731bb76ff1Sjsg 		if (ret)
2741bb76ff1Sjsg 			return ret;
2751bb76ff1Sjsg 	}
276c349dbc7Sjsg 
277c349dbc7Sjsg 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
278c349dbc7Sjsg 		return -EINVAL;
279c349dbc7Sjsg 
280*f005ef32Sjsg 	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
281c349dbc7Sjsg 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
282c349dbc7Sjsg 
283c349dbc7Sjsg 	return 0;
284c349dbc7Sjsg }
285c349dbc7Sjsg 
intel_dvo_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)286ad8b1aafSjsg static void intel_dvo_pre_enable(struct intel_atomic_state *state,
287ad8b1aafSjsg 				 struct intel_encoder *encoder,
288c349dbc7Sjsg 				 const struct intel_crtc_state *pipe_config,
289c349dbc7Sjsg 				 const struct drm_connector_state *conn_state)
290c349dbc7Sjsg {
291*f005ef32Sjsg 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
292c349dbc7Sjsg 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
293c349dbc7Sjsg 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
294*f005ef32Sjsg 	enum port port = encoder->port;
295c349dbc7Sjsg 	enum pipe pipe = crtc->pipe;
296c349dbc7Sjsg 	u32 dvo_val;
297c349dbc7Sjsg 
298*f005ef32Sjsg 	/* Save the active data order, since I don't know what it should be set to. */
299*f005ef32Sjsg 	dvo_val = intel_de_read(i915, DVO(port)) &
300*f005ef32Sjsg 		  (DVO_DEDICATED_INT_ENABLE |
301*f005ef32Sjsg 		   DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_MASK);
302c349dbc7Sjsg 	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
303c349dbc7Sjsg 		   DVO_BLANK_ACTIVE_HIGH;
304c349dbc7Sjsg 
305c349dbc7Sjsg 	dvo_val |= DVO_PIPE_SEL(pipe);
306c349dbc7Sjsg 	dvo_val |= DVO_PIPE_STALL;
307c349dbc7Sjsg 	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
308c349dbc7Sjsg 		dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
309c349dbc7Sjsg 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
310c349dbc7Sjsg 		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
311c349dbc7Sjsg 
312*f005ef32Sjsg 	intel_de_write(i915, DVO_SRCDIM(port),
313*f005ef32Sjsg 		       DVO_SRCDIM_HORIZONTAL(adjusted_mode->crtc_hdisplay) |
314*f005ef32Sjsg 		       DVO_SRCDIM_VERTICAL(adjusted_mode->crtc_vdisplay));
315*f005ef32Sjsg 	intel_de_write(i915, DVO(port), dvo_val);
316c349dbc7Sjsg }
317c349dbc7Sjsg 
318c349dbc7Sjsg static enum drm_connector_status
intel_dvo_detect(struct drm_connector * _connector,bool force)319*f005ef32Sjsg intel_dvo_detect(struct drm_connector *_connector, bool force)
320c349dbc7Sjsg {
321*f005ef32Sjsg 	struct intel_connector *connector = to_intel_connector(_connector);
322*f005ef32Sjsg 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
323*f005ef32Sjsg 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
324ad8b1aafSjsg 
325*f005ef32Sjsg 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
326*f005ef32Sjsg 		    connector->base.base.id, connector->base.name);
327ad8b1aafSjsg 
328ad8b1aafSjsg 	if (!INTEL_DISPLAY_ENABLED(i915))
329ad8b1aafSjsg 		return connector_status_disconnected;
330ad8b1aafSjsg 
331c349dbc7Sjsg 	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
332c349dbc7Sjsg }
333c349dbc7Sjsg 
intel_dvo_get_modes(struct drm_connector * _connector)334*f005ef32Sjsg static int intel_dvo_get_modes(struct drm_connector *_connector)
335c349dbc7Sjsg {
336*f005ef32Sjsg 	struct intel_connector *connector = to_intel_connector(_connector);
337*f005ef32Sjsg 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
338ad8b1aafSjsg 	int num_modes;
339c349dbc7Sjsg 
340c349dbc7Sjsg 	/*
341c349dbc7Sjsg 	 * We should probably have an i2c driver get_modes function for those
342c349dbc7Sjsg 	 * devices which will have a fixed set of modes determined by the chip
343c349dbc7Sjsg 	 * (TV-out, for example), but for now with just TMDS and LVDS,
344c349dbc7Sjsg 	 * that's not the case.
345c349dbc7Sjsg 	 */
346*f005ef32Sjsg 	num_modes = intel_ddc_get_modes(&connector->base,
347*f005ef32Sjsg 					intel_gmbus_get_adapter(i915, GMBUS_PIN_DPC));
348ad8b1aafSjsg 	if (num_modes)
349ad8b1aafSjsg 		return num_modes;
350c349dbc7Sjsg 
351*f005ef32Sjsg 	return intel_panel_get_modes(connector);
352c349dbc7Sjsg }
353c349dbc7Sjsg 
354c349dbc7Sjsg static const struct drm_connector_funcs intel_dvo_connector_funcs = {
355c349dbc7Sjsg 	.detect = intel_dvo_detect,
356c349dbc7Sjsg 	.late_register = intel_connector_register,
357c349dbc7Sjsg 	.early_unregister = intel_connector_unregister,
358c349dbc7Sjsg 	.destroy = intel_connector_destroy,
359c349dbc7Sjsg 	.fill_modes = drm_helper_probe_single_connector_modes,
360c349dbc7Sjsg 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
361c349dbc7Sjsg 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
362c349dbc7Sjsg };
363c349dbc7Sjsg 
364c349dbc7Sjsg static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
365c349dbc7Sjsg 	.mode_valid = intel_dvo_mode_valid,
366c349dbc7Sjsg 	.get_modes = intel_dvo_get_modes,
367c349dbc7Sjsg };
368c349dbc7Sjsg 
intel_dvo_enc_destroy(struct drm_encoder * encoder)369c349dbc7Sjsg static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
370c349dbc7Sjsg {
371c349dbc7Sjsg 	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));
372c349dbc7Sjsg 
373c349dbc7Sjsg 	if (intel_dvo->dev.dev_ops->destroy)
374c349dbc7Sjsg 		intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
375c349dbc7Sjsg 
376c349dbc7Sjsg 	intel_encoder_destroy(encoder);
377c349dbc7Sjsg }
378c349dbc7Sjsg 
379c349dbc7Sjsg static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
380c349dbc7Sjsg 	.destroy = intel_dvo_enc_destroy,
381c349dbc7Sjsg };
382c349dbc7Sjsg 
intel_dvo_encoder_type(const struct intel_dvo_device * dvo)383*f005ef32Sjsg static int intel_dvo_encoder_type(const struct intel_dvo_device *dvo)
384c349dbc7Sjsg {
385*f005ef32Sjsg 	switch (dvo->type) {
386*f005ef32Sjsg 	case INTEL_DVO_CHIP_TMDS:
387*f005ef32Sjsg 		return DRM_MODE_ENCODER_TMDS;
388*f005ef32Sjsg 	case INTEL_DVO_CHIP_LVDS_NO_FIXED:
389*f005ef32Sjsg 	case INTEL_DVO_CHIP_LVDS:
390*f005ef32Sjsg 		return DRM_MODE_ENCODER_LVDS;
391*f005ef32Sjsg 	default:
392*f005ef32Sjsg 		MISSING_CASE(dvo->type);
393*f005ef32Sjsg 		return DRM_MODE_ENCODER_NONE;
394*f005ef32Sjsg 	}
395c349dbc7Sjsg }
396c349dbc7Sjsg 
intel_dvo_connector_type(const struct intel_dvo_device * dvo)397*f005ef32Sjsg static int intel_dvo_connector_type(const struct intel_dvo_device *dvo)
398c349dbc7Sjsg {
399*f005ef32Sjsg 	switch (dvo->type) {
400*f005ef32Sjsg 	case INTEL_DVO_CHIP_TMDS:
401*f005ef32Sjsg 		return DRM_MODE_CONNECTOR_DVII;
402*f005ef32Sjsg 	case INTEL_DVO_CHIP_LVDS_NO_FIXED:
403*f005ef32Sjsg 	case INTEL_DVO_CHIP_LVDS:
404*f005ef32Sjsg 		return DRM_MODE_CONNECTOR_LVDS;
405*f005ef32Sjsg 	default:
406*f005ef32Sjsg 		MISSING_CASE(dvo->type);
407*f005ef32Sjsg 		return DRM_MODE_CONNECTOR_Unknown;
408*f005ef32Sjsg 	}
409c349dbc7Sjsg }
410c349dbc7Sjsg 
intel_dvo_init_dev(struct drm_i915_private * dev_priv,struct intel_dvo * intel_dvo,const struct intel_dvo_device * dvo)411*f005ef32Sjsg static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
412*f005ef32Sjsg 			       struct intel_dvo *intel_dvo,
413*f005ef32Sjsg 			       const struct intel_dvo_device *dvo)
414*f005ef32Sjsg {
415c349dbc7Sjsg 	struct i2c_adapter *i2c;
416c349dbc7Sjsg 	u32 dpll[I915_MAX_PIPES];
417*f005ef32Sjsg 	enum pipe pipe;
418*f005ef32Sjsg 	int gpio;
419*f005ef32Sjsg 	bool ret;
420c349dbc7Sjsg 
421c349dbc7Sjsg 	/*
422c349dbc7Sjsg 	 * Allow the I2C driver info to specify the GPIO to be used in
423c349dbc7Sjsg 	 * special cases, but otherwise default to what's defined
424c349dbc7Sjsg 	 * in the spec.
425c349dbc7Sjsg 	 */
426c349dbc7Sjsg 	if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
427c349dbc7Sjsg 		gpio = dvo->gpio;
428c349dbc7Sjsg 	else if (dvo->type == INTEL_DVO_CHIP_LVDS)
429c349dbc7Sjsg 		gpio = GMBUS_PIN_SSC;
430c349dbc7Sjsg 	else
431c349dbc7Sjsg 		gpio = GMBUS_PIN_DPB;
432c349dbc7Sjsg 
433c349dbc7Sjsg 	/*
434c349dbc7Sjsg 	 * Set up the I2C bus necessary for the chip we're probing.
435c349dbc7Sjsg 	 * It appears that everything is on GPIOE except for panels
436c349dbc7Sjsg 	 * on i830 laptops, which are on GPIOB (DVOA).
437c349dbc7Sjsg 	 */
438c349dbc7Sjsg 	i2c = intel_gmbus_get_adapter(dev_priv, gpio);
439c349dbc7Sjsg 
440c349dbc7Sjsg 	intel_dvo->dev = *dvo;
441c349dbc7Sjsg 
442c349dbc7Sjsg 	/*
443c349dbc7Sjsg 	 * GMBUS NAK handling seems to be unstable, hence let the
444c349dbc7Sjsg 	 * transmitter detection run in bit banging mode for now.
445c349dbc7Sjsg 	 */
446c349dbc7Sjsg 	intel_gmbus_force_bit(i2c, true);
447c349dbc7Sjsg 
448c349dbc7Sjsg 	/*
449c349dbc7Sjsg 	 * ns2501 requires the DVO 2x clock before it will
450c349dbc7Sjsg 	 * respond to i2c accesses, so make sure we have
451*f005ef32Sjsg 	 * the clock enabled before we attempt to initialize
452*f005ef32Sjsg 	 * the device.
453c349dbc7Sjsg 	 */
454*f005ef32Sjsg 	for_each_pipe(dev_priv, pipe)
455*f005ef32Sjsg 		dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE);
456c349dbc7Sjsg 
457*f005ef32Sjsg 	ret = dvo->dev_ops->init(&intel_dvo->dev, i2c);
458c349dbc7Sjsg 
459c349dbc7Sjsg 	/* restore the DVO 2x clock state to original */
460c349dbc7Sjsg 	for_each_pipe(dev_priv, pipe) {
461c349dbc7Sjsg 		intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]);
462c349dbc7Sjsg 	}
463c349dbc7Sjsg 
464c349dbc7Sjsg 	intel_gmbus_force_bit(i2c, false);
465c349dbc7Sjsg 
466*f005ef32Sjsg 	return ret;
467c349dbc7Sjsg }
468c349dbc7Sjsg 
intel_dvo_probe(struct drm_i915_private * i915,struct intel_dvo * intel_dvo)469*f005ef32Sjsg static bool intel_dvo_probe(struct drm_i915_private *i915,
470*f005ef32Sjsg 			    struct intel_dvo *intel_dvo)
471*f005ef32Sjsg {
472*f005ef32Sjsg 	int i;
473c349dbc7Sjsg 
474*f005ef32Sjsg 	/* Now, try to find a controller */
475*f005ef32Sjsg 	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
476*f005ef32Sjsg 		if (intel_dvo_init_dev(i915, intel_dvo,
477*f005ef32Sjsg 				       &intel_dvo_devices[i]))
478*f005ef32Sjsg 			return true;
479*f005ef32Sjsg 	}
480*f005ef32Sjsg 
481*f005ef32Sjsg 	return false;
482*f005ef32Sjsg }
483*f005ef32Sjsg 
intel_dvo_init(struct drm_i915_private * i915)484*f005ef32Sjsg void intel_dvo_init(struct drm_i915_private *i915)
485*f005ef32Sjsg {
486*f005ef32Sjsg 	struct intel_connector *connector;
487*f005ef32Sjsg 	struct intel_encoder *encoder;
488*f005ef32Sjsg 	struct intel_dvo *intel_dvo;
489*f005ef32Sjsg 
490*f005ef32Sjsg 	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
491*f005ef32Sjsg 	if (!intel_dvo)
492*f005ef32Sjsg 		return;
493*f005ef32Sjsg 
494*f005ef32Sjsg 	connector = intel_connector_alloc();
495*f005ef32Sjsg 	if (!connector) {
496*f005ef32Sjsg 		kfree(intel_dvo);
497*f005ef32Sjsg 		return;
498*f005ef32Sjsg 	}
499*f005ef32Sjsg 
500*f005ef32Sjsg 	intel_dvo->attached_connector = connector;
501*f005ef32Sjsg 
502*f005ef32Sjsg 	encoder = &intel_dvo->base;
503*f005ef32Sjsg 
504*f005ef32Sjsg 	encoder->disable = intel_disable_dvo;
505*f005ef32Sjsg 	encoder->enable = intel_enable_dvo;
506*f005ef32Sjsg 	encoder->get_hw_state = intel_dvo_get_hw_state;
507*f005ef32Sjsg 	encoder->get_config = intel_dvo_get_config;
508*f005ef32Sjsg 	encoder->compute_config = intel_dvo_compute_config;
509*f005ef32Sjsg 	encoder->pre_enable = intel_dvo_pre_enable;
510*f005ef32Sjsg 	connector->get_hw_state = intel_dvo_connector_get_hw_state;
511*f005ef32Sjsg 
512*f005ef32Sjsg 	if (!intel_dvo_probe(i915, intel_dvo)) {
513*f005ef32Sjsg 		kfree(intel_dvo);
514*f005ef32Sjsg 		intel_connector_free(connector);
515*f005ef32Sjsg 		return;
516*f005ef32Sjsg 	}
517*f005ef32Sjsg 
518*f005ef32Sjsg 	assert_port_valid(i915, intel_dvo->dev.port);
519*f005ef32Sjsg 
520*f005ef32Sjsg 	encoder->type = INTEL_OUTPUT_DVO;
521*f005ef32Sjsg 	encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
522*f005ef32Sjsg 	encoder->port = intel_dvo->dev.port;
523*f005ef32Sjsg 	encoder->pipe_mask = ~0;
524*f005ef32Sjsg 
525*f005ef32Sjsg 	if (intel_dvo->dev.type != INTEL_DVO_CHIP_LVDS)
526*f005ef32Sjsg 		encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG) |
527*f005ef32Sjsg 			BIT(INTEL_OUTPUT_DVO);
528*f005ef32Sjsg 
529*f005ef32Sjsg 	drm_encoder_init(&i915->drm, &encoder->base,
530*f005ef32Sjsg 			 &intel_dvo_enc_funcs,
531*f005ef32Sjsg 			 intel_dvo_encoder_type(&intel_dvo->dev),
532*f005ef32Sjsg 			 "DVO %c", port_name(encoder->port));
533*f005ef32Sjsg 
534*f005ef32Sjsg 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] detected %s\n",
535*f005ef32Sjsg 		    encoder->base.base.id, encoder->base.name,
536*f005ef32Sjsg 		    intel_dvo->dev.name);
537*f005ef32Sjsg 
538*f005ef32Sjsg 	if (intel_dvo->dev.type == INTEL_DVO_CHIP_TMDS)
539*f005ef32Sjsg 		connector->polled = DRM_CONNECTOR_POLL_CONNECT |
540*f005ef32Sjsg 			DRM_CONNECTOR_POLL_DISCONNECT;
541*f005ef32Sjsg 
542*f005ef32Sjsg 	drm_connector_init(&i915->drm, &connector->base,
543*f005ef32Sjsg 			   &intel_dvo_connector_funcs,
544*f005ef32Sjsg 			   intel_dvo_connector_type(&intel_dvo->dev));
545*f005ef32Sjsg 
546*f005ef32Sjsg 	drm_connector_helper_add(&connector->base,
547*f005ef32Sjsg 				 &intel_dvo_connector_helper_funcs);
548*f005ef32Sjsg 	connector->base.display_info.subpixel_order = SubPixelHorizontalRGB;
549*f005ef32Sjsg 
550*f005ef32Sjsg 	intel_connector_attach_encoder(connector, encoder);
551*f005ef32Sjsg 
552*f005ef32Sjsg 	if (intel_dvo->dev.type == INTEL_DVO_CHIP_LVDS) {
553c349dbc7Sjsg 		/*
554c349dbc7Sjsg 		 * For our LVDS chipsets, we should hopefully be able
555c349dbc7Sjsg 		 * to dig the fixed panel mode out of the BIOS data.
556c349dbc7Sjsg 		 * However, it's in a different format from the BIOS
557c349dbc7Sjsg 		 * data on chipsets with integrated LVDS (stored in AIM
558c349dbc7Sjsg 		 * headers, likely), so for now, just get the current
559c349dbc7Sjsg 		 * mode being output through DVO.
560c349dbc7Sjsg 		 */
561*f005ef32Sjsg 		intel_panel_add_encoder_fixed_mode(connector, encoder);
5621bb76ff1Sjsg 
563*f005ef32Sjsg 		intel_panel_init(connector, NULL);
564c349dbc7Sjsg 	}
565c349dbc7Sjsg }
566