xref: /openbsd-src/sys/dev/pci/drm/amd/include/atom-names.h (revision fb4d85023675bc7da402da96b2bb84fd12905dbf)
1*fb4d8502Sjsg /*
2*fb4d8502Sjsg  * Copyright 2008 Advanced Micro Devices, Inc.
3*fb4d8502Sjsg  *
4*fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5*fb4d8502Sjsg  * copy of this software and associated documentation files (the "Software"),
6*fb4d8502Sjsg  * to deal in the Software without restriction, including without limitation
7*fb4d8502Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*fb4d8502Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9*fb4d8502Sjsg  * Software is furnished to do so, subject to the following conditions:
10*fb4d8502Sjsg  *
11*fb4d8502Sjsg  * The above copyright notice and this permission notice shall be included in
12*fb4d8502Sjsg  * all copies or substantial portions of the Software.
13*fb4d8502Sjsg  *
14*fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*fb4d8502Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*fb4d8502Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*fb4d8502Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*fb4d8502Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21*fb4d8502Sjsg  *
22*fb4d8502Sjsg  * Author: Stanislaw Skowronek
23*fb4d8502Sjsg  */
24*fb4d8502Sjsg 
25*fb4d8502Sjsg #ifndef ATOM_NAMES_H
26*fb4d8502Sjsg #define ATOM_NAMES_H
27*fb4d8502Sjsg 
28*fb4d8502Sjsg #include "atom.h"
29*fb4d8502Sjsg 
30*fb4d8502Sjsg #ifdef ATOM_DEBUG
31*fb4d8502Sjsg 
32*fb4d8502Sjsg #define ATOM_OP_NAMES_CNT 123
33*fb4d8502Sjsg static char *atom_op_names[ATOM_OP_NAMES_CNT] = {
34*fb4d8502Sjsg "RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
35*fb4d8502Sjsg "MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
36*fb4d8502Sjsg "OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
37*fb4d8502Sjsg "SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
38*fb4d8502Sjsg "SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
39*fb4d8502Sjsg "SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
40*fb4d8502Sjsg "MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
41*fb4d8502Sjsg "DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
42*fb4d8502Sjsg "ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
43*fb4d8502Sjsg "SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
44*fb4d8502Sjsg "SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
45*fb4d8502Sjsg "COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
46*fb4d8502Sjsg "JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
47*fb4d8502Sjsg "JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
48*fb4d8502Sjsg "TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
49*fb4d8502Sjsg "CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
50*fb4d8502Sjsg "CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
51*fb4d8502Sjsg "MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
52*fb4d8502Sjsg "RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
53*fb4d8502Sjsg "XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
54*fb4d8502Sjsg "SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
55*fb4d8502Sjsg "DEBUG", "CTB_DS",
56*fb4d8502Sjsg };
57*fb4d8502Sjsg 
58*fb4d8502Sjsg #define ATOM_TABLE_NAMES_CNT 74
59*fb4d8502Sjsg static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
60*fb4d8502Sjsg "ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
61*fb4d8502Sjsg "VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
62*fb4d8502Sjsg "GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
63*fb4d8502Sjsg "GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
64*fb4d8502Sjsg "DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
65*fb4d8502Sjsg "MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
66*fb4d8502Sjsg "EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
67*fb4d8502Sjsg "DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
68*fb4d8502Sjsg "DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
69*fb4d8502Sjsg "CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
70*fb4d8502Sjsg "TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
71*fb4d8502Sjsg "EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
72*fb4d8502Sjsg "EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
73*fb4d8502Sjsg "SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
74*fb4d8502Sjsg "EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
75*fb4d8502Sjsg "LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
76*fb4d8502Sjsg "GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
77*fb4d8502Sjsg "DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
78*fb4d8502Sjsg "ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
79*fb4d8502Sjsg "ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
80*fb4d8502Sjsg "MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
81*fb4d8502Sjsg "VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
82*fb4d8502Sjsg "EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
83*fb4d8502Sjsg "CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
84*fb4d8502Sjsg "MemoryDeviceInit", "EnableYUV",
85*fb4d8502Sjsg };
86*fb4d8502Sjsg 
87*fb4d8502Sjsg #define ATOM_IO_NAMES_CNT 5
88*fb4d8502Sjsg static char *atom_io_names[ATOM_IO_NAMES_CNT] = {
89*fb4d8502Sjsg "MM", "PLL", "MC", "PCIE", "PCIE PORT",
90*fb4d8502Sjsg };
91*fb4d8502Sjsg 
92*fb4d8502Sjsg #else
93*fb4d8502Sjsg 
94*fb4d8502Sjsg #define ATOM_OP_NAMES_CNT 0
95*fb4d8502Sjsg #define ATOM_TABLE_NAMES_CNT 0
96*fb4d8502Sjsg #define ATOM_IO_NAMES_CNT 0
97*fb4d8502Sjsg 
98*fb4d8502Sjsg #endif
99*fb4d8502Sjsg 
100*fb4d8502Sjsg #endif
101