1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2015 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg */ 22fb4d8502Sjsg 23fb4d8502Sjsg #ifndef __AMD_PCIE_H__ 24fb4d8502Sjsg #define __AMD_PCIE_H__ 25fb4d8502Sjsg 26fb4d8502Sjsg /* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */ 27fb4d8502Sjsg #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000 28fb4d8502Sjsg #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000 29fb4d8502Sjsg #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000 30fb4d8502Sjsg #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000 31*5ca02815Sjsg #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00100000 32fb4d8502Sjsg #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000 33fb4d8502Sjsg #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16 34fb4d8502Sjsg 35fb4d8502Sjsg /* Following flags shows PCIe link speed supported by ASIC H/W.*/ 36fb4d8502Sjsg #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001 37fb4d8502Sjsg #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002 38fb4d8502Sjsg #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004 39fb4d8502Sjsg #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008 40*5ca02815Sjsg #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00000010 41fb4d8502Sjsg #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF 42fb4d8502Sjsg #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0 43fb4d8502Sjsg 44fb4d8502Sjsg /* gen: chipset 1/2, asic 1/2/3 */ 45fb4d8502Sjsg #define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \ 46fb4d8502Sjsg | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \ 47fb4d8502Sjsg | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \ 48fb4d8502Sjsg | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \ 49fb4d8502Sjsg | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3) 50fb4d8502Sjsg 51fb4d8502Sjsg /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */ 52fb4d8502Sjsg #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000 53fb4d8502Sjsg #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000 54fb4d8502Sjsg #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000 55fb4d8502Sjsg #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000 56fb4d8502Sjsg #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000 57fb4d8502Sjsg #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000 58fb4d8502Sjsg #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000 59fb4d8502Sjsg #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16 60fb4d8502Sjsg 61fb4d8502Sjsg /* 1/2/4/8/16 lanes */ 62fb4d8502Sjsg #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \ 63fb4d8502Sjsg | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \ 64fb4d8502Sjsg | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \ 65fb4d8502Sjsg | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \ 66fb4d8502Sjsg | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 67fb4d8502Sjsg 68fb4d8502Sjsg #endif 69