1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2012 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg */ 23fb4d8502Sjsg 24fb4d8502Sjsg #ifndef AMD_ACPI_H 25fb4d8502Sjsg #define AMD_ACPI_H 26fb4d8502Sjsg 27fb4d8502Sjsg #define ACPI_AC_CLASS "ac_adapter" 28fb4d8502Sjsg 29fb4d8502Sjsg struct atif_verify_interface { 30fb4d8502Sjsg u16 size; /* structure size in bytes (includes size field) */ 31fb4d8502Sjsg u16 version; /* version */ 32fb4d8502Sjsg u32 notification_mask; /* supported notifications mask */ 33fb4d8502Sjsg u32 function_bits; /* supported functions bit vector */ 34fb4d8502Sjsg } __packed; 35fb4d8502Sjsg 36fb4d8502Sjsg struct atif_system_params { 37fb4d8502Sjsg u16 size; /* structure size in bytes (includes size field) */ 38fb4d8502Sjsg u32 valid_mask; /* valid flags mask */ 39fb4d8502Sjsg u32 flags; /* flags */ 40fb4d8502Sjsg u8 command_code; /* notify command code */ 41fb4d8502Sjsg } __packed; 42fb4d8502Sjsg 43fb4d8502Sjsg struct atif_sbios_requests { 44fb4d8502Sjsg u16 size; /* structure size in bytes (includes size field) */ 45fb4d8502Sjsg u32 pending; /* pending sbios requests */ 46fb4d8502Sjsg u8 panel_exp_mode; /* panel expansion mode */ 47fb4d8502Sjsg u8 thermal_gfx; /* thermal state: target gfx controller */ 48fb4d8502Sjsg u8 thermal_state; /* thermal state: state id (0: exit state, non-0: state) */ 49fb4d8502Sjsg u8 forced_power_gfx; /* forced power state: target gfx controller */ 50fb4d8502Sjsg u8 forced_power_state; /* forced power state: state id */ 51fb4d8502Sjsg u8 system_power_src; /* system power source */ 52fb4d8502Sjsg u8 backlight_level; /* panel backlight level (0-255) */ 53fb4d8502Sjsg } __packed; 54fb4d8502Sjsg 55c349dbc7Sjsg struct atif_qbtc_arguments { 56c349dbc7Sjsg u16 size; /* structure size in bytes (includes size field) */ 57c349dbc7Sjsg u8 requested_display; /* which display is requested */ 58c349dbc7Sjsg } __packed; 59c349dbc7Sjsg 60c349dbc7Sjsg #define ATIF_QBTC_MAX_DATA_POINTS 99 61c349dbc7Sjsg 62c349dbc7Sjsg struct atif_qbtc_data_point { 63c349dbc7Sjsg u8 luminance; /* luminance in percent */ 64c349dbc7Sjsg u8 ipnut_signal; /* input signal in range 0-255 */ 65c349dbc7Sjsg } __packed; 66c349dbc7Sjsg 67c349dbc7Sjsg struct atif_qbtc_output { 68c349dbc7Sjsg u16 size; /* structure size in bytes (includes size field) */ 69c349dbc7Sjsg u16 flags; /* all zeroes */ 70c349dbc7Sjsg u8 error_code; /* error code */ 71c349dbc7Sjsg u8 ac_level; /* default brightness on AC power */ 72c349dbc7Sjsg u8 dc_level; /* default brightness on DC power */ 73c349dbc7Sjsg u8 min_input_signal; /* max input signal in range 0-255 */ 74c349dbc7Sjsg u8 max_input_signal; /* min input signal in range 0-255 */ 75c349dbc7Sjsg u8 number_of_points; /* number of data points */ 76c349dbc7Sjsg struct atif_qbtc_data_point data_points[ATIF_QBTC_MAX_DATA_POINTS]; 77c349dbc7Sjsg } __packed; 78c349dbc7Sjsg 79fb4d8502Sjsg #define ATIF_NOTIFY_MASK 0x3 80fb4d8502Sjsg #define ATIF_NOTIFY_NONE 0 81fb4d8502Sjsg #define ATIF_NOTIFY_81 1 82fb4d8502Sjsg #define ATIF_NOTIFY_N 2 83fb4d8502Sjsg 84fb4d8502Sjsg struct atcs_verify_interface { 85fb4d8502Sjsg u16 size; /* structure size in bytes (includes size field) */ 86fb4d8502Sjsg u16 version; /* version */ 87fb4d8502Sjsg u32 function_bits; /* supported functions bit vector */ 88fb4d8502Sjsg } __packed; 89fb4d8502Sjsg 90fb4d8502Sjsg #define ATCS_VALID_FLAGS_MASK 0x3 91fb4d8502Sjsg 92fb4d8502Sjsg struct atcs_pref_req_input { 93fb4d8502Sjsg u16 size; /* structure size in bytes (includes size field) */ 94fb4d8502Sjsg u16 client_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ 95fb4d8502Sjsg u16 valid_flags_mask; /* valid flags mask */ 96fb4d8502Sjsg u16 flags; /* flags */ 97fb4d8502Sjsg u8 req_type; /* request type */ 98fb4d8502Sjsg u8 perf_req; /* performance request */ 99fb4d8502Sjsg } __packed; 100fb4d8502Sjsg 101fb4d8502Sjsg struct atcs_pref_req_output { 102fb4d8502Sjsg u16 size; /* structure size in bytes (includes size field) */ 103fb4d8502Sjsg u8 ret_val; /* return value */ 104fb4d8502Sjsg } __packed; 105fb4d8502Sjsg 106*5ca02815Sjsg struct atcs_pwr_shift_input { 107*5ca02815Sjsg u16 size; /* structure size in bytes (includes size field) */ 108*5ca02815Sjsg u16 dgpu_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ 109*5ca02815Sjsg u8 dev_acpi_state; /* D0 = 0, D3 hot = 3 */ 110*5ca02815Sjsg u8 drv_state; /* 0 = operational, 1 = not operational */ 111*5ca02815Sjsg } __packed; 112*5ca02815Sjsg 113fb4d8502Sjsg /* AMD hw uses four ACPI control methods: 114fb4d8502Sjsg * 1. ATIF 115fb4d8502Sjsg * ARG0: (ACPI_INTEGER) function code 116fb4d8502Sjsg * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes 117fb4d8502Sjsg * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes 118fb4d8502Sjsg * ATIF provides an entry point for the gfx driver to interact with the sbios. 119fb4d8502Sjsg * The AMD ACPI notification mechanism uses Notify (VGA, 0x81) or a custom 120fb4d8502Sjsg * notification. Which notification is used as indicated by the ATIF Control 121fb4d8502Sjsg * Method GET_SYSTEM_PARAMETERS. When the driver receives Notify (VGA, 0x81) or 122fb4d8502Sjsg * a custom notification it invokes ATIF Control Method GET_SYSTEM_BIOS_REQUESTS 123fb4d8502Sjsg * to identify pending System BIOS requests and associated parameters. For 124fb4d8502Sjsg * example, if one of the pending requests is DISPLAY_SWITCH_REQUEST, the driver 125fb4d8502Sjsg * will perform display device detection and invoke ATIF Control Method 126fb4d8502Sjsg * SELECT_ACTIVE_DISPLAYS. 127fb4d8502Sjsg * 128fb4d8502Sjsg * 2. ATPX 129fb4d8502Sjsg * ARG0: (ACPI_INTEGER) function code 130fb4d8502Sjsg * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes 131fb4d8502Sjsg * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes 132fb4d8502Sjsg * ATPX methods are used on PowerXpress systems to handle mux switching and 133fb4d8502Sjsg * discrete GPU power control. 134fb4d8502Sjsg * 135fb4d8502Sjsg * 3. ATRM 136fb4d8502Sjsg * ARG0: (ACPI_INTEGER) offset of vbios rom data 137fb4d8502Sjsg * ARG1: (ACPI_BUFFER) size of the buffer to fill (up to 4K). 138fb4d8502Sjsg * OUTPUT: (ACPI_BUFFER) output buffer 139fb4d8502Sjsg * ATRM provides an interfacess to access the discrete GPU vbios image on 140fb4d8502Sjsg * PowerXpress systems with multiple GPUs. 141fb4d8502Sjsg * 142fb4d8502Sjsg * 4. ATCS 143fb4d8502Sjsg * ARG0: (ACPI_INTEGER) function code 144fb4d8502Sjsg * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes 145fb4d8502Sjsg * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes 146fb4d8502Sjsg * ATCS provides an interface to AMD chipset specific functionality. 147fb4d8502Sjsg * 148fb4d8502Sjsg */ 149fb4d8502Sjsg /* ATIF */ 150fb4d8502Sjsg #define ATIF_FUNCTION_VERIFY_INTERFACE 0x0 151fb4d8502Sjsg /* ARG0: ATIF_FUNCTION_VERIFY_INTERFACE 152fb4d8502Sjsg * ARG1: none 153fb4d8502Sjsg * OUTPUT: 154fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 155fb4d8502Sjsg * WORD - version 156fb4d8502Sjsg * DWORD - supported notifications mask 157fb4d8502Sjsg * DWORD - supported functions bit vector 158fb4d8502Sjsg */ 159fb4d8502Sjsg /* Notifications mask */ 160fb4d8502Sjsg # define ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED (1 << 2) 161fb4d8502Sjsg # define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED (1 << 3) 162fb4d8502Sjsg # define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED (1 << 4) 163fb4d8502Sjsg # define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED (1 << 7) 164fb4d8502Sjsg # define ATIF_DGPU_DISPLAY_EVENT_SUPPORTED (1 << 8) 165c349dbc7Sjsg # define ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST_SUPPORTED (1 << 12) 166fb4d8502Sjsg /* supported functions vector */ 167fb4d8502Sjsg # define ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED (1 << 0) 168fb4d8502Sjsg # define ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED (1 << 1) 169fb4d8502Sjsg # define ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED (1 << 12) 170c349dbc7Sjsg # define ATIF_QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS_SUPPORTED (1 << 15) 171c349dbc7Sjsg # define ATIF_READY_TO_UNDOCK_NOTIFICATION_SUPPORTED (1 << 16) 172fb4d8502Sjsg # define ATIF_GET_EXTERNAL_GPU_INFORMATION_SUPPORTED (1 << 20) 173fb4d8502Sjsg #define ATIF_FUNCTION_GET_SYSTEM_PARAMETERS 0x1 174fb4d8502Sjsg /* ARG0: ATIF_FUNCTION_GET_SYSTEM_PARAMETERS 175fb4d8502Sjsg * ARG1: none 176fb4d8502Sjsg * OUTPUT: 177fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 178fb4d8502Sjsg * DWORD - valid flags mask 179fb4d8502Sjsg * DWORD - flags 180fb4d8502Sjsg * 181fb4d8502Sjsg * OR 182fb4d8502Sjsg * 183fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 184fb4d8502Sjsg * DWORD - valid flags mask 185fb4d8502Sjsg * DWORD - flags 186fb4d8502Sjsg * BYTE - notify command code 187fb4d8502Sjsg * 188fb4d8502Sjsg * flags 189fb4d8502Sjsg * bits 1:0: 190fb4d8502Sjsg * 0 - Notify(VGA, 0x81) is not used for notification 191fb4d8502Sjsg * 1 - Notify(VGA, 0x81) is used for notification 192fb4d8502Sjsg * 2 - Notify(VGA, n) is used for notification where 193fb4d8502Sjsg * n (0xd0-0xd9) is specified in notify command code. 194fb4d8502Sjsg * bit 2: 195fb4d8502Sjsg * 1 - lid changes not reported though int10 196c349dbc7Sjsg * bit 3: 197c349dbc7Sjsg * 1 - system bios controls overclocking 198c349dbc7Sjsg * bit 4: 199c349dbc7Sjsg * 1 - enable overclocking 200fb4d8502Sjsg */ 201fb4d8502Sjsg #define ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS 0x2 202fb4d8502Sjsg /* ARG0: ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS 203fb4d8502Sjsg * ARG1: none 204fb4d8502Sjsg * OUTPUT: 205fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 206fb4d8502Sjsg * DWORD - pending sbios requests 207c349dbc7Sjsg * BYTE - reserved (all zeroes) 208fb4d8502Sjsg * BYTE - thermal state: target gfx controller 209fb4d8502Sjsg * BYTE - thermal state: state id (0: exit state, non-0: state) 210fb4d8502Sjsg * BYTE - forced power state: target gfx controller 211c349dbc7Sjsg * BYTE - forced power state: state id (0: forced state, non-0: state) 212fb4d8502Sjsg * BYTE - system power source 213fb4d8502Sjsg * BYTE - panel backlight level (0-255) 214c349dbc7Sjsg * BYTE - GPU package power limit: target gfx controller 215c349dbc7Sjsg * DWORD - GPU package power limit: value (24:8 fractional format, Watts) 216fb4d8502Sjsg */ 217fb4d8502Sjsg /* pending sbios requests */ 218fb4d8502Sjsg # define ATIF_THERMAL_STATE_CHANGE_REQUEST (1 << 2) 219fb4d8502Sjsg # define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST (1 << 3) 220fb4d8502Sjsg # define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST (1 << 4) 221fb4d8502Sjsg # define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST (1 << 7) 222fb4d8502Sjsg # define ATIF_DGPU_DISPLAY_EVENT (1 << 8) 223c349dbc7Sjsg # define ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST (1 << 12) 224fb4d8502Sjsg /* target gfx controller */ 225fb4d8502Sjsg # define ATIF_TARGET_GFX_SINGLE 0 226fb4d8502Sjsg # define ATIF_TARGET_GFX_PX_IGPU 1 227fb4d8502Sjsg # define ATIF_TARGET_GFX_PX_DGPU 2 228fb4d8502Sjsg /* system power source */ 229fb4d8502Sjsg # define ATIF_POWER_SOURCE_AC 1 230fb4d8502Sjsg # define ATIF_POWER_SOURCE_DC 2 231fb4d8502Sjsg # define ATIF_POWER_SOURCE_RESTRICTED_AC_1 3 232fb4d8502Sjsg # define ATIF_POWER_SOURCE_RESTRICTED_AC_2 4 233fb4d8502Sjsg #define ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION 0xD 234fb4d8502Sjsg /* ARG0: ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION 235fb4d8502Sjsg * ARG1: 236fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 237fb4d8502Sjsg * WORD - gfx controller id 238fb4d8502Sjsg * BYTE - current temperature (degress Celsius) 239fb4d8502Sjsg * OUTPUT: none 240fb4d8502Sjsg */ 241c349dbc7Sjsg #define ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS 0x10 242c349dbc7Sjsg /* ARG0: ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS 243c349dbc7Sjsg * ARG1: 244c349dbc7Sjsg * WORD - structure size in bytes (includes size field) 245c349dbc7Sjsg * BYTE - requested display 246fb4d8502Sjsg * OUTPUT: 247c349dbc7Sjsg * WORD - structure size in bytes (includes size field) 248c349dbc7Sjsg * WORD - flags (currently all 16 bits are reserved) 249c349dbc7Sjsg * BYTE - error code (on failure, disregard all below fields) 250c349dbc7Sjsg * BYTE - AC level (default brightness in percent when machine has full power) 251c349dbc7Sjsg * BYTE - DC level (default brightness in percent when machine is on battery) 252c349dbc7Sjsg * BYTE - min input signal, in range 0-255, corresponding to 0% backlight 253c349dbc7Sjsg * BYTE - max input signal, in range 0-255, corresponding to 100% backlight 254c349dbc7Sjsg * BYTE - number of reported data points 255c349dbc7Sjsg * BYTE - luminance level in percent \ repeated structure 256c349dbc7Sjsg * BYTE - input signal in range 0-255 / does not have entries for 0% and 100% 257fb4d8502Sjsg */ 258c349dbc7Sjsg /* requested display */ 259c349dbc7Sjsg # define ATIF_QBTC_REQUEST_LCD1 0 260c349dbc7Sjsg # define ATIF_QBTC_REQUEST_CRT1 1 261c349dbc7Sjsg # define ATIF_QBTC_REQUEST_DFP1 3 262c349dbc7Sjsg # define ATIF_QBTC_REQUEST_CRT2 4 263c349dbc7Sjsg # define ATIF_QBTC_REQUEST_LCD2 5 264c349dbc7Sjsg # define ATIF_QBTC_REQUEST_DFP2 7 265c349dbc7Sjsg # define ATIF_QBTC_REQUEST_DFP3 9 266c349dbc7Sjsg # define ATIF_QBTC_REQUEST_DFP4 10 267c349dbc7Sjsg # define ATIF_QBTC_REQUEST_DFP5 11 268c349dbc7Sjsg # define ATIF_QBTC_REQUEST_DFP6 12 269c349dbc7Sjsg /* error code */ 270c349dbc7Sjsg # define ATIF_QBTC_ERROR_CODE_SUCCESS 0 271c349dbc7Sjsg # define ATIF_QBTC_ERROR_CODE_FAILURE 1 272c349dbc7Sjsg # define ATIF_QBTC_ERROR_CODE_DEVICE_NOT_SUPPORTED 2 273c349dbc7Sjsg #define ATIF_FUNCTION_READY_TO_UNDOCK_NOTIFICATION 0x11 274c349dbc7Sjsg /* ARG0: ATIF_FUNCTION_READY_TO_UNDOCK_NOTIFICATION 275c349dbc7Sjsg * ARG1: none 276c349dbc7Sjsg * OUTPUT: none 277c349dbc7Sjsg */ 278fb4d8502Sjsg #define ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION 0x15 279fb4d8502Sjsg /* ARG0: ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION 280fb4d8502Sjsg * ARG1: none 281fb4d8502Sjsg * OUTPUT: 282fb4d8502Sjsg * WORD - number of reported external gfx devices 283fb4d8502Sjsg * WORD - device structure size in bytes (excludes device size field) 284fb4d8502Sjsg * WORD - flags \ 285fb4d8502Sjsg * WORD - bus number / repeated structure 286fb4d8502Sjsg */ 287fb4d8502Sjsg /* flags */ 288fb4d8502Sjsg # define ATIF_EXTERNAL_GRAPHICS_PORT (1 << 0) 289fb4d8502Sjsg 290fb4d8502Sjsg /* ATPX */ 291fb4d8502Sjsg #define ATPX_FUNCTION_VERIFY_INTERFACE 0x0 292fb4d8502Sjsg /* ARG0: ATPX_FUNCTION_VERIFY_INTERFACE 293fb4d8502Sjsg * ARG1: none 294fb4d8502Sjsg * OUTPUT: 295fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 296fb4d8502Sjsg * WORD - version 297fb4d8502Sjsg * DWORD - supported functions bit vector 298fb4d8502Sjsg */ 299fb4d8502Sjsg /* supported functions vector */ 300fb4d8502Sjsg # define ATPX_GET_PX_PARAMETERS_SUPPORTED (1 << 0) 301fb4d8502Sjsg # define ATPX_POWER_CONTROL_SUPPORTED (1 << 1) 302fb4d8502Sjsg # define ATPX_DISPLAY_MUX_CONTROL_SUPPORTED (1 << 2) 303fb4d8502Sjsg # define ATPX_I2C_MUX_CONTROL_SUPPORTED (1 << 3) 304fb4d8502Sjsg # define ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED (1 << 4) 305fb4d8502Sjsg # define ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED (1 << 5) 306fb4d8502Sjsg # define ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED (1 << 7) 307fb4d8502Sjsg # define ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED (1 << 8) 308fb4d8502Sjsg #define ATPX_FUNCTION_GET_PX_PARAMETERS 0x1 309fb4d8502Sjsg /* ARG0: ATPX_FUNCTION_GET_PX_PARAMETERS 310fb4d8502Sjsg * ARG1: none 311fb4d8502Sjsg * OUTPUT: 312fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 313fb4d8502Sjsg * DWORD - valid flags mask 314fb4d8502Sjsg * DWORD - flags 315fb4d8502Sjsg */ 316fb4d8502Sjsg /* flags */ 317fb4d8502Sjsg # define ATPX_LVDS_I2C_AVAILABLE_TO_BOTH_GPUS (1 << 0) 318fb4d8502Sjsg # define ATPX_CRT1_I2C_AVAILABLE_TO_BOTH_GPUS (1 << 1) 319fb4d8502Sjsg # define ATPX_DVI1_I2C_AVAILABLE_TO_BOTH_GPUS (1 << 2) 320fb4d8502Sjsg # define ATPX_CRT1_RGB_SIGNAL_MUXED (1 << 3) 321fb4d8502Sjsg # define ATPX_TV_SIGNAL_MUXED (1 << 4) 322fb4d8502Sjsg # define ATPX_DFP_SIGNAL_MUXED (1 << 5) 323fb4d8502Sjsg # define ATPX_SEPARATE_MUX_FOR_I2C (1 << 6) 324fb4d8502Sjsg # define ATPX_DYNAMIC_PX_SUPPORTED (1 << 7) 325fb4d8502Sjsg # define ATPX_ACF_NOT_SUPPORTED (1 << 8) 326fb4d8502Sjsg # define ATPX_FIXED_NOT_SUPPORTED (1 << 9) 327fb4d8502Sjsg # define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED (1 << 10) 328fb4d8502Sjsg # define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS (1 << 11) 329fb4d8502Sjsg # define ATPX_DGPU_CAN_DRIVE_DISPLAYS (1 << 12) 330fb4d8502Sjsg # define ATPX_MS_HYBRID_GFX_SUPPORTED (1 << 14) 331fb4d8502Sjsg #define ATPX_FUNCTION_POWER_CONTROL 0x2 332fb4d8502Sjsg /* ARG0: ATPX_FUNCTION_POWER_CONTROL 333fb4d8502Sjsg * ARG1: 334fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 335fb4d8502Sjsg * BYTE - dGPU power state (0: power off, 1: power on) 336fb4d8502Sjsg * OUTPUT: none 337fb4d8502Sjsg */ 338fb4d8502Sjsg #define ATPX_FUNCTION_DISPLAY_MUX_CONTROL 0x3 339fb4d8502Sjsg /* ARG0: ATPX_FUNCTION_DISPLAY_MUX_CONTROL 340fb4d8502Sjsg * ARG1: 341fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 342fb4d8502Sjsg * WORD - display mux control (0: iGPU, 1: dGPU) 343fb4d8502Sjsg * OUTPUT: none 344fb4d8502Sjsg */ 345fb4d8502Sjsg # define ATPX_INTEGRATED_GPU 0 346fb4d8502Sjsg # define ATPX_DISCRETE_GPU 1 347fb4d8502Sjsg #define ATPX_FUNCTION_I2C_MUX_CONTROL 0x4 348fb4d8502Sjsg /* ARG0: ATPX_FUNCTION_I2C_MUX_CONTROL 349fb4d8502Sjsg * ARG1: 350fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 351fb4d8502Sjsg * WORD - i2c/aux/hpd mux control (0: iGPU, 1: dGPU) 352fb4d8502Sjsg * OUTPUT: none 353fb4d8502Sjsg */ 354fb4d8502Sjsg #define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION 0x5 355fb4d8502Sjsg /* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION 356fb4d8502Sjsg * ARG1: 357fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 358fb4d8502Sjsg * WORD - target gpu (0: iGPU, 1: dGPU) 359fb4d8502Sjsg * OUTPUT: none 360fb4d8502Sjsg */ 361fb4d8502Sjsg #define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION 0x6 362fb4d8502Sjsg /* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION 363fb4d8502Sjsg * ARG1: 364fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 365fb4d8502Sjsg * WORD - target gpu (0: iGPU, 1: dGPU) 366fb4d8502Sjsg * OUTPUT: none 367fb4d8502Sjsg */ 368fb4d8502Sjsg #define ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING 0x8 369fb4d8502Sjsg /* ARG0: ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING 370fb4d8502Sjsg * ARG1: none 371fb4d8502Sjsg * OUTPUT: 372fb4d8502Sjsg * WORD - number of display connectors 373fb4d8502Sjsg * WORD - connector structure size in bytes (excludes connector size field) 374fb4d8502Sjsg * BYTE - flags \ 375fb4d8502Sjsg * BYTE - ATIF display vector bit position } repeated 376fb4d8502Sjsg * BYTE - adapter id (0: iGPU, 1-n: dGPU ordered by pcie bus number) } structure 377fb4d8502Sjsg * WORD - connector ACPI id / 378fb4d8502Sjsg */ 379fb4d8502Sjsg /* flags */ 380fb4d8502Sjsg # define ATPX_DISPLAY_OUTPUT_SUPPORTED_BY_ADAPTER_ID_DEVICE (1 << 0) 381fb4d8502Sjsg # define ATPX_DISPLAY_HPD_SUPPORTED_BY_ADAPTER_ID_DEVICE (1 << 1) 382fb4d8502Sjsg # define ATPX_DISPLAY_I2C_SUPPORTED_BY_ADAPTER_ID_DEVICE (1 << 2) 383fb4d8502Sjsg #define ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS 0x9 384fb4d8502Sjsg /* ARG0: ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS 385fb4d8502Sjsg * ARG1: none 386fb4d8502Sjsg * OUTPUT: 387fb4d8502Sjsg * WORD - number of HPD/DDC ports 388fb4d8502Sjsg * WORD - port structure size in bytes (excludes port size field) 389fb4d8502Sjsg * BYTE - ATIF display vector bit position \ 390fb4d8502Sjsg * BYTE - hpd id } reapeated structure 391fb4d8502Sjsg * BYTE - ddc id / 392fb4d8502Sjsg * 393fb4d8502Sjsg * available on A+A systems only 394fb4d8502Sjsg */ 395fb4d8502Sjsg /* hpd id */ 396fb4d8502Sjsg # define ATPX_HPD_NONE 0 397fb4d8502Sjsg # define ATPX_HPD1 1 398fb4d8502Sjsg # define ATPX_HPD2 2 399fb4d8502Sjsg # define ATPX_HPD3 3 400fb4d8502Sjsg # define ATPX_HPD4 4 401fb4d8502Sjsg # define ATPX_HPD5 5 402fb4d8502Sjsg # define ATPX_HPD6 6 403fb4d8502Sjsg /* ddc id */ 404fb4d8502Sjsg # define ATPX_DDC_NONE 0 405fb4d8502Sjsg # define ATPX_DDC1 1 406fb4d8502Sjsg # define ATPX_DDC2 2 407fb4d8502Sjsg # define ATPX_DDC3 3 408fb4d8502Sjsg # define ATPX_DDC4 4 409fb4d8502Sjsg # define ATPX_DDC5 5 410fb4d8502Sjsg # define ATPX_DDC6 6 411fb4d8502Sjsg # define ATPX_DDC7 7 412fb4d8502Sjsg # define ATPX_DDC8 8 413fb4d8502Sjsg 414fb4d8502Sjsg /* ATCS */ 415fb4d8502Sjsg #define ATCS_FUNCTION_VERIFY_INTERFACE 0x0 416fb4d8502Sjsg /* ARG0: ATCS_FUNCTION_VERIFY_INTERFACE 417fb4d8502Sjsg * ARG1: none 418fb4d8502Sjsg * OUTPUT: 419fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 420fb4d8502Sjsg * WORD - version 421fb4d8502Sjsg * DWORD - supported functions bit vector 422fb4d8502Sjsg */ 423fb4d8502Sjsg /* supported functions vector */ 424fb4d8502Sjsg # define ATCS_GET_EXTERNAL_STATE_SUPPORTED (1 << 0) 425fb4d8502Sjsg # define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED (1 << 1) 426fb4d8502Sjsg # define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED (1 << 2) 427fb4d8502Sjsg # define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED (1 << 3) 428*5ca02815Sjsg # define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED (1 << 7) 429fb4d8502Sjsg #define ATCS_FUNCTION_GET_EXTERNAL_STATE 0x1 430fb4d8502Sjsg /* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE 431fb4d8502Sjsg * ARG1: none 432fb4d8502Sjsg * OUTPUT: 433fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 434fb4d8502Sjsg * DWORD - valid flags mask 435fb4d8502Sjsg * DWORD - flags (0: undocked, 1: docked) 436fb4d8502Sjsg */ 437fb4d8502Sjsg /* flags */ 438fb4d8502Sjsg # define ATCS_DOCKED (1 << 0) 439fb4d8502Sjsg #define ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST 0x2 440fb4d8502Sjsg /* ARG0: ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST 441fb4d8502Sjsg * ARG1: 442fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 443fb4d8502Sjsg * WORD - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) 444fb4d8502Sjsg * WORD - valid flags mask 445fb4d8502Sjsg * WORD - flags 446fb4d8502Sjsg * BYTE - request type 447fb4d8502Sjsg * BYTE - performance request 448fb4d8502Sjsg * OUTPUT: 449fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 450fb4d8502Sjsg * BYTE - return value 451fb4d8502Sjsg */ 452fb4d8502Sjsg /* flags */ 453fb4d8502Sjsg # define ATCS_ADVERTISE_CAPS (1 << 0) 454fb4d8502Sjsg # define ATCS_WAIT_FOR_COMPLETION (1 << 1) 455fb4d8502Sjsg /* request type */ 456fb4d8502Sjsg # define ATCS_PCIE_LINK_SPEED 1 457fb4d8502Sjsg /* performance request */ 458fb4d8502Sjsg # define ATCS_REMOVE 0 459fb4d8502Sjsg # define ATCS_FORCE_LOW_POWER 1 460fb4d8502Sjsg # define ATCS_PERF_LEVEL_1 2 /* PCIE Gen 1 */ 461fb4d8502Sjsg # define ATCS_PERF_LEVEL_2 3 /* PCIE Gen 2 */ 462fb4d8502Sjsg # define ATCS_PERF_LEVEL_3 4 /* PCIE Gen 3 */ 463fb4d8502Sjsg /* return value */ 464fb4d8502Sjsg # define ATCS_REQUEST_REFUSED 1 465fb4d8502Sjsg # define ATCS_REQUEST_COMPLETE 2 466fb4d8502Sjsg # define ATCS_REQUEST_IN_PROGRESS 3 467fb4d8502Sjsg #define ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION 0x3 468fb4d8502Sjsg /* ARG0: ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION 469fb4d8502Sjsg * ARG1: none 470fb4d8502Sjsg * OUTPUT: none 471fb4d8502Sjsg */ 472fb4d8502Sjsg #define ATCS_FUNCTION_SET_PCIE_BUS_WIDTH 0x4 473fb4d8502Sjsg /* ARG0: ATCS_FUNCTION_SET_PCIE_BUS_WIDTH 474fb4d8502Sjsg * ARG1: 475fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 476fb4d8502Sjsg * WORD - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) 477fb4d8502Sjsg * BYTE - number of active lanes 478fb4d8502Sjsg * OUTPUT: 479fb4d8502Sjsg * WORD - structure size in bytes (includes size field) 480fb4d8502Sjsg * BYTE - number of active lanes 481fb4d8502Sjsg */ 482fb4d8502Sjsg 483*5ca02815Sjsg #define ATCS_FUNCTION_POWER_SHIFT_CONTROL 0x8 484*5ca02815Sjsg /* ARG0: ATCS_FUNCTION_POWER_SHIFT_CONTROL 485*5ca02815Sjsg * ARG1: 486*5ca02815Sjsg * WORD - structure size in bytes (includes size field) 487*5ca02815Sjsg * WORD - dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) 488*5ca02815Sjsg * BYTE - Device ACPI state 489*5ca02815Sjsg * BYTE - Driver state 490*5ca02815Sjsg * OUTPUT: none 491*5ca02815Sjsg */ 492*5ca02815Sjsg 493fb4d8502Sjsg #endif 494