1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2012-15 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg * Authors: AMD 23fb4d8502Sjsg * 24fb4d8502Sjsg */ 25fb4d8502Sjsg 26fb4d8502Sjsg /** 27fb4d8502Sjsg * This file defines helper functions provided by the Display Manager to 28fb4d8502Sjsg * Display Core. 29fb4d8502Sjsg */ 30fb4d8502Sjsg #ifndef __DM_HELPERS__ 31fb4d8502Sjsg #define __DM_HELPERS__ 32fb4d8502Sjsg 33fb4d8502Sjsg #include "dc_types.h" 34fb4d8502Sjsg #include "dc.h" 35fb4d8502Sjsg 361bb76ff1Sjsg struct dc_dp_mst_stream_allocation_table; 375ca02815Sjsg struct aux_payload; 385ca02815Sjsg enum aux_return_code_type; 39fb4d8502Sjsg 40ad8b1aafSjsg /* 41ad8b1aafSjsg * Allocate memory accessible by the GPU 42ad8b1aafSjsg * 43ad8b1aafSjsg * frame buffer allocations must be aligned to a 4096-byte boundary 44ad8b1aafSjsg * 45ad8b1aafSjsg * Returns virtual address, sets addr to physical address 46ad8b1aafSjsg */ 47ad8b1aafSjsg void *dm_helpers_allocate_gpu_mem( 48ad8b1aafSjsg struct dc_context *ctx, 49ad8b1aafSjsg enum dc_gpu_mem_alloc_type type, 50ad8b1aafSjsg size_t size, 51ad8b1aafSjsg long long *addr); 52ad8b1aafSjsg 53ad8b1aafSjsg /* 54ad8b1aafSjsg * Free the GPU-accessible memory at the virtual address pvMem 55ad8b1aafSjsg */ 56ad8b1aafSjsg void dm_helpers_free_gpu_mem( 57ad8b1aafSjsg struct dc_context *ctx, 58ad8b1aafSjsg enum dc_gpu_mem_alloc_type type, 59ad8b1aafSjsg void *pvMem); 60ad8b1aafSjsg 61fb4d8502Sjsg enum dc_edid_status dm_helpers_parse_edid_caps( 621bb76ff1Sjsg struct dc_link *link, 63fb4d8502Sjsg const struct dc_edid *edid, 64fb4d8502Sjsg struct dc_edid_caps *edid_caps); 65fb4d8502Sjsg 66fb4d8502Sjsg 67fb4d8502Sjsg /* 68fb4d8502Sjsg * Update DP branch info 69fb4d8502Sjsg */ 70fb4d8502Sjsg void dm_helpers_dp_update_branch_info( 71fb4d8502Sjsg struct dc_context *ctx, 72fb4d8502Sjsg const struct dc_link *link); 73fb4d8502Sjsg 74fb4d8502Sjsg /* 75fb4d8502Sjsg * Writes payload allocation table in immediate downstream device. 76fb4d8502Sjsg */ 77fb4d8502Sjsg bool dm_helpers_dp_mst_write_payload_allocation_table( 78fb4d8502Sjsg struct dc_context *ctx, 79fb4d8502Sjsg const struct dc_stream_state *stream, 801bb76ff1Sjsg struct dc_dp_mst_stream_allocation_table *proposed_table, 81fb4d8502Sjsg bool enable); 82fb4d8502Sjsg 83fb4d8502Sjsg /* 84c349dbc7Sjsg * poll pending down reply 85c349dbc7Sjsg */ 86c349dbc7Sjsg void dm_helpers_dp_mst_poll_pending_down_reply( 87c349dbc7Sjsg struct dc_context *ctx, 88c349dbc7Sjsg const struct dc_link *link); 89c349dbc7Sjsg 90c349dbc7Sjsg /* 91fb4d8502Sjsg * Clear payload allocation table before enable MST DP link. 92fb4d8502Sjsg */ 93fb4d8502Sjsg void dm_helpers_dp_mst_clear_payload_allocation_table( 94fb4d8502Sjsg struct dc_context *ctx, 95fb4d8502Sjsg const struct dc_link *link); 96fb4d8502Sjsg 97fb4d8502Sjsg /* 98fb4d8502Sjsg * Polls for ACT (allocation change trigger) handled and 99fb4d8502Sjsg */ 100c349dbc7Sjsg enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 101fb4d8502Sjsg struct dc_context *ctx, 102fb4d8502Sjsg const struct dc_stream_state *stream); 103fb4d8502Sjsg /* 104fb4d8502Sjsg * Sends ALLOCATE_PAYLOAD message. 105fb4d8502Sjsg */ 106fb4d8502Sjsg bool dm_helpers_dp_mst_send_payload_allocation( 107fb4d8502Sjsg struct dc_context *ctx, 108fb4d8502Sjsg const struct dc_stream_state *stream, 109fb4d8502Sjsg bool enable); 110fb4d8502Sjsg 111fb4d8502Sjsg bool dm_helpers_dp_mst_start_top_mgr( 112fb4d8502Sjsg struct dc_context *ctx, 113fb4d8502Sjsg const struct dc_link *link, 114fb4d8502Sjsg bool boot); 115fb4d8502Sjsg 1161bb76ff1Sjsg bool dm_helpers_dp_mst_stop_top_mgr( 117fb4d8502Sjsg struct dc_context *ctx, 1185ca02815Sjsg struct dc_link *link); 119*f005ef32Sjsg 120*f005ef32Sjsg void dm_helpers_dp_mst_update_branch_bandwidth( 121*f005ef32Sjsg struct dc_context *ctx, 122*f005ef32Sjsg struct dc_link *link); 123*f005ef32Sjsg 124fb4d8502Sjsg /** 125fb4d8502Sjsg * OS specific aux read callback. 126fb4d8502Sjsg */ 127fb4d8502Sjsg bool dm_helpers_dp_read_dpcd( 128fb4d8502Sjsg struct dc_context *ctx, 129fb4d8502Sjsg const struct dc_link *link, 130fb4d8502Sjsg uint32_t address, 131fb4d8502Sjsg uint8_t *data, 132fb4d8502Sjsg uint32_t size); 133fb4d8502Sjsg 134fb4d8502Sjsg /** 135fb4d8502Sjsg * OS specific aux write callback. 136fb4d8502Sjsg */ 137fb4d8502Sjsg bool dm_helpers_dp_write_dpcd( 138fb4d8502Sjsg struct dc_context *ctx, 139fb4d8502Sjsg const struct dc_link *link, 140fb4d8502Sjsg uint32_t address, 141fb4d8502Sjsg const uint8_t *data, 142fb4d8502Sjsg uint32_t size); 143fb4d8502Sjsg 144fb4d8502Sjsg bool dm_helpers_submit_i2c( 145fb4d8502Sjsg struct dc_context *ctx, 146fb4d8502Sjsg const struct dc_link *link, 147fb4d8502Sjsg struct i2c_command *cmd); 148fb4d8502Sjsg 149c349dbc7Sjsg bool dm_helpers_dp_write_dsc_enable( 150c349dbc7Sjsg struct dc_context *ctx, 151c349dbc7Sjsg const struct dc_stream_state *stream, 152c349dbc7Sjsg bool enable 153c349dbc7Sjsg ); 154fb4d8502Sjsg bool dm_helpers_is_dp_sink_present( 155fb4d8502Sjsg struct dc_link *link); 156fb4d8502Sjsg 1575ca02815Sjsg void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream); 1585ca02815Sjsg 159fb4d8502Sjsg enum dc_edid_status dm_helpers_read_local_edid( 160fb4d8502Sjsg struct dc_context *ctx, 161fb4d8502Sjsg struct dc_link *link, 162fb4d8502Sjsg struct dc_sink *sink); 163fb4d8502Sjsg 164cd357bb4Sjsg bool dm_helpers_dp_handle_test_pattern_request( 165cd357bb4Sjsg struct dc_context *ctx, 166cd357bb4Sjsg const struct dc_link *link, 167cd357bb4Sjsg union link_test_pattern dpcd_test_pattern, 168cd357bb4Sjsg union test_misc dpcd_test_params); 169cd357bb4Sjsg 170fb4d8502Sjsg void dm_set_dcn_clocks( 171fb4d8502Sjsg struct dc_context *ctx, 172fb4d8502Sjsg struct dc_clocks *clks); 173fb4d8502Sjsg 1741bb76ff1Sjsg void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable); 1751bb76ff1Sjsg 1761bb76ff1Sjsg void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz); 1771bb76ff1Sjsg 1785ca02815Sjsg bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable); 1795ca02815Sjsg 1805ca02815Sjsg void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us); 1815ca02815Sjsg 1821bb76ff1Sjsg // 0x1 = Result_OK, 0xFE = Result_UnkmownCmd, 0x0 = Status_Busy 1835ca02815Sjsg #define IS_SMU_TIMEOUT(result) \ 1841bb76ff1Sjsg (result == 0x0) 1851bb76ff1Sjsg void dm_helpers_init_panel_settings( 1861bb76ff1Sjsg struct dc_context *ctx, 1871bb76ff1Sjsg struct dc_panel_config *config, 1881bb76ff1Sjsg struct dc_sink *sink); 1891bb76ff1Sjsg void dm_helpers_override_panel_settings( 1901bb76ff1Sjsg struct dc_context *ctx, 1911bb76ff1Sjsg struct dc_panel_config *config); 1925ca02815Sjsg int dm_helper_dmub_aux_transfer_sync( 1935ca02815Sjsg struct dc_context *ctx, 1945ca02815Sjsg const struct dc_link *link, 1955ca02815Sjsg struct aux_payload *payload, 1965ca02815Sjsg enum aux_return_code_type *operation_result); 1971bb76ff1Sjsg enum set_config_status; 1981bb76ff1Sjsg int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 1991bb76ff1Sjsg const struct dc_link *link, 2001bb76ff1Sjsg struct set_config_cmd_payload *payload, 2011bb76ff1Sjsg enum set_config_status *operation_result); 202*f005ef32Sjsg enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link); 2031bb76ff1Sjsg 2041bb76ff1Sjsg enum dc_edid_status dm_helpers_get_sbios_edid(struct dc_link *link, struct dc_edid *edid); 2051bb76ff1Sjsg 206fb4d8502Sjsg #endif /* __DM_HELPERS__ */ 207