xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/tonga_ih.c (revision f7a572c71fb97b89c2743970c49baa8a12be8057)
1fb4d8502Sjsg /*
2fb4d8502Sjsg  * Copyright 2014 Advanced Micro Devices, Inc.
3fb4d8502Sjsg  *
4fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg  * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg  * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg  * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg  *
11fb4d8502Sjsg  * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg  * all copies or substantial portions of the Software.
13fb4d8502Sjsg  *
14fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17fb4d8502Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg  *
22fb4d8502Sjsg  */
23c349dbc7Sjsg 
24c349dbc7Sjsg #include <linux/pci.h>
25c349dbc7Sjsg 
26fb4d8502Sjsg #include "amdgpu.h"
27fb4d8502Sjsg #include "amdgpu_ih.h"
28fb4d8502Sjsg #include "vid.h"
29fb4d8502Sjsg 
30fb4d8502Sjsg #include "oss/oss_3_0_d.h"
31fb4d8502Sjsg #include "oss/oss_3_0_sh_mask.h"
32fb4d8502Sjsg 
33fb4d8502Sjsg #include "bif/bif_5_1_d.h"
34fb4d8502Sjsg #include "bif/bif_5_1_sh_mask.h"
35fb4d8502Sjsg 
36fb4d8502Sjsg /*
37fb4d8502Sjsg  * Interrupts
38fb4d8502Sjsg  * Starting with r6xx, interrupts are handled via a ring buffer.
39fb4d8502Sjsg  * Ring buffers are areas of GPU accessible memory that the GPU
40fb4d8502Sjsg  * writes interrupt vectors into and the host reads vectors out of.
41fb4d8502Sjsg  * There is a rptr (read pointer) that determines where the
42fb4d8502Sjsg  * host is currently reading, and a wptr (write pointer)
43fb4d8502Sjsg  * which determines where the GPU has written.  When the
44fb4d8502Sjsg  * pointers are equal, the ring is idle.  When the GPU
45fb4d8502Sjsg  * writes vectors to the ring buffer, it increments the
46fb4d8502Sjsg  * wptr.  When there is an interrupt, the host then starts
47fb4d8502Sjsg  * fetching commands and processing them until the pointers are
48fb4d8502Sjsg  * equal again at which point it updates the rptr.
49fb4d8502Sjsg  */
50fb4d8502Sjsg 
51fb4d8502Sjsg static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
52fb4d8502Sjsg 
53fb4d8502Sjsg /**
54fb4d8502Sjsg  * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
55fb4d8502Sjsg  *
56fb4d8502Sjsg  * @adev: amdgpu_device pointer
57fb4d8502Sjsg  *
58fb4d8502Sjsg  * Enable the interrupt ring buffer (VI).
59fb4d8502Sjsg  */
tonga_ih_enable_interrupts(struct amdgpu_device * adev)60fb4d8502Sjsg static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
61fb4d8502Sjsg {
62fb4d8502Sjsg 	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
63fb4d8502Sjsg 
64fb4d8502Sjsg 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
65fb4d8502Sjsg 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
66fb4d8502Sjsg 	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
67fb4d8502Sjsg 	adev->irq.ih.enabled = true;
68fb4d8502Sjsg }
69fb4d8502Sjsg 
70fb4d8502Sjsg /**
71fb4d8502Sjsg  * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
72fb4d8502Sjsg  *
73fb4d8502Sjsg  * @adev: amdgpu_device pointer
74fb4d8502Sjsg  *
75fb4d8502Sjsg  * Disable the interrupt ring buffer (VI).
76fb4d8502Sjsg  */
tonga_ih_disable_interrupts(struct amdgpu_device * adev)77fb4d8502Sjsg static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
78fb4d8502Sjsg {
79fb4d8502Sjsg 	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
80fb4d8502Sjsg 
81fb4d8502Sjsg 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
82fb4d8502Sjsg 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
83fb4d8502Sjsg 	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
84fb4d8502Sjsg 	/* set rptr, wptr to 0 */
85fb4d8502Sjsg 	WREG32(mmIH_RB_RPTR, 0);
86fb4d8502Sjsg 	WREG32(mmIH_RB_WPTR, 0);
87fb4d8502Sjsg 	adev->irq.ih.enabled = false;
88fb4d8502Sjsg 	adev->irq.ih.rptr = 0;
89fb4d8502Sjsg }
90fb4d8502Sjsg 
91fb4d8502Sjsg /**
92fb4d8502Sjsg  * tonga_ih_irq_init - init and enable the interrupt ring
93fb4d8502Sjsg  *
94fb4d8502Sjsg  * @adev: amdgpu_device pointer
95fb4d8502Sjsg  *
96fb4d8502Sjsg  * Allocate a ring buffer for the interrupt controller,
97fb4d8502Sjsg  * enable the RLC, disable interrupts, enable the IH
98fb4d8502Sjsg  * ring buffer and enable it (VI).
99fb4d8502Sjsg  * Called at device load and reume.
100fb4d8502Sjsg  * Returns 0 for success, errors for failure.
101fb4d8502Sjsg  */
tonga_ih_irq_init(struct amdgpu_device * adev)102fb4d8502Sjsg static int tonga_ih_irq_init(struct amdgpu_device *adev)
103fb4d8502Sjsg {
104fb4d8502Sjsg 	u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
105c349dbc7Sjsg 	struct amdgpu_ih_ring *ih = &adev->irq.ih;
106c349dbc7Sjsg 	int rb_bufsz;
107fb4d8502Sjsg 
108fb4d8502Sjsg 	/* disable irqs */
109fb4d8502Sjsg 	tonga_ih_disable_interrupts(adev);
110fb4d8502Sjsg 
111fb4d8502Sjsg 	/* setup interrupt control */
112fb4d8502Sjsg 	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
113fb4d8502Sjsg 	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
114fb4d8502Sjsg 	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
115fb4d8502Sjsg 	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
116fb4d8502Sjsg 	 */
117fb4d8502Sjsg 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
118fb4d8502Sjsg 	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
119fb4d8502Sjsg 	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
120fb4d8502Sjsg 	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
121fb4d8502Sjsg 
122fb4d8502Sjsg 	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
123c349dbc7Sjsg 	WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
124fb4d8502Sjsg 
125fb4d8502Sjsg 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
126fb4d8502Sjsg 	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
127fb4d8502Sjsg 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
128fb4d8502Sjsg 	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
129fb4d8502Sjsg 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
130fb4d8502Sjsg 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
131fb4d8502Sjsg 
132fb4d8502Sjsg 	if (adev->irq.msi_enabled)
133fb4d8502Sjsg 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
134fb4d8502Sjsg 
135fb4d8502Sjsg 	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
136fb4d8502Sjsg 
137fb4d8502Sjsg 	/* set the writeback address whether it's enabled or not */
138c349dbc7Sjsg 	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
139c349dbc7Sjsg 	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
140fb4d8502Sjsg 
141fb4d8502Sjsg 	/* set rptr, wptr to 0 */
142fb4d8502Sjsg 	WREG32(mmIH_RB_RPTR, 0);
143fb4d8502Sjsg 	WREG32(mmIH_RB_WPTR, 0);
144fb4d8502Sjsg 
145fb4d8502Sjsg 	ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
146fb4d8502Sjsg 	if (adev->irq.ih.use_doorbell) {
147fb4d8502Sjsg 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
148fb4d8502Sjsg 						 OFFSET, adev->irq.ih.doorbell_index);
149fb4d8502Sjsg 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
150fb4d8502Sjsg 						 ENABLE, 1);
151fb4d8502Sjsg 	} else {
152fb4d8502Sjsg 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
153fb4d8502Sjsg 						 ENABLE, 0);
154fb4d8502Sjsg 	}
155fb4d8502Sjsg 	WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
156fb4d8502Sjsg 
157fb4d8502Sjsg 	pci_set_master(adev->pdev);
158fb4d8502Sjsg 
159fb4d8502Sjsg 	/* enable interrupts */
160fb4d8502Sjsg 	tonga_ih_enable_interrupts(adev);
161fb4d8502Sjsg 
162fb4d8502Sjsg 	return 0;
163fb4d8502Sjsg }
164fb4d8502Sjsg 
165fb4d8502Sjsg /**
166fb4d8502Sjsg  * tonga_ih_irq_disable - disable interrupts
167fb4d8502Sjsg  *
168fb4d8502Sjsg  * @adev: amdgpu_device pointer
169fb4d8502Sjsg  *
170fb4d8502Sjsg  * Disable interrupts on the hw (VI).
171fb4d8502Sjsg  */
tonga_ih_irq_disable(struct amdgpu_device * adev)172fb4d8502Sjsg static void tonga_ih_irq_disable(struct amdgpu_device *adev)
173fb4d8502Sjsg {
174fb4d8502Sjsg 	tonga_ih_disable_interrupts(adev);
175fb4d8502Sjsg 
176fb4d8502Sjsg 	/* Wait and acknowledge irq */
177fb4d8502Sjsg 	mdelay(1);
178fb4d8502Sjsg }
179fb4d8502Sjsg 
180fb4d8502Sjsg /**
181fb4d8502Sjsg  * tonga_ih_get_wptr - get the IH ring buffer wptr
182fb4d8502Sjsg  *
183fb4d8502Sjsg  * @adev: amdgpu_device pointer
1845ca02815Sjsg  * @ih: IH ring buffer to fetch wptr
185fb4d8502Sjsg  *
186fb4d8502Sjsg  * Get the IH ring buffer wptr from either the register
187fb4d8502Sjsg  * or the writeback memory buffer (VI).  Also check for
188fb4d8502Sjsg  * ring buffer overflow and deal with it.
189fb4d8502Sjsg  * Used by cz_irq_process(VI).
190fb4d8502Sjsg  * Returns the value of the wptr.
191fb4d8502Sjsg  */
tonga_ih_get_wptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)192c349dbc7Sjsg static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
193c349dbc7Sjsg 			     struct amdgpu_ih_ring *ih)
194fb4d8502Sjsg {
195fb4d8502Sjsg 	u32 wptr, tmp;
196fb4d8502Sjsg 
197c349dbc7Sjsg 	wptr = le32_to_cpu(*ih->wptr_cpu);
198fb4d8502Sjsg 
199ad8b1aafSjsg 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
200ad8b1aafSjsg 		goto out;
201ad8b1aafSjsg 
202ad8b1aafSjsg 	/* Double check that the overflow wasn't already cleared. */
203ad8b1aafSjsg 	wptr = RREG32(mmIH_RB_WPTR);
204ad8b1aafSjsg 
205ad8b1aafSjsg 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
206ad8b1aafSjsg 		goto out;
207ad8b1aafSjsg 
208fb4d8502Sjsg 	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
209ad8b1aafSjsg 
210fb4d8502Sjsg 	/* When a ring buffer overflow happen start parsing interrupt
211fb4d8502Sjsg 	 * from the last not overwritten vector (wptr + 16). Hopefully
212fb4d8502Sjsg 	 * this should allow us to catchup.
213fb4d8502Sjsg 	 */
214ad8b1aafSjsg 
215fb4d8502Sjsg 	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
216c349dbc7Sjsg 		wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
217c349dbc7Sjsg 	ih->rptr = (wptr + 16) & ih->ptr_mask;
218fb4d8502Sjsg 	tmp = RREG32(mmIH_RB_CNTL);
219fb4d8502Sjsg 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
220fb4d8502Sjsg 	WREG32(mmIH_RB_CNTL, tmp);
221ad8b1aafSjsg 
222*f7a572c7Sjsg 	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
223*f7a572c7Sjsg 	 * can be detected.
224*f7a572c7Sjsg 	 */
225*f7a572c7Sjsg 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
226*f7a572c7Sjsg 	WREG32(mmIH_RB_CNTL, tmp);
227*f7a572c7Sjsg 
228ad8b1aafSjsg out:
229c349dbc7Sjsg 	return (wptr & ih->ptr_mask);
230fb4d8502Sjsg }
231fb4d8502Sjsg 
232fb4d8502Sjsg /**
233fb4d8502Sjsg  * tonga_ih_decode_iv - decode an interrupt vector
234fb4d8502Sjsg  *
235fb4d8502Sjsg  * @adev: amdgpu_device pointer
2365ca02815Sjsg  * @ih: IH ring buffer to decode
2375ca02815Sjsg  * @entry: IV entry to place decoded information into
238fb4d8502Sjsg  *
239fb4d8502Sjsg  * Decodes the interrupt vector at the current rptr
240fb4d8502Sjsg  * position and also advance the position.
241fb4d8502Sjsg  */
tonga_ih_decode_iv(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,struct amdgpu_iv_entry * entry)242fb4d8502Sjsg static void tonga_ih_decode_iv(struct amdgpu_device *adev,
243c349dbc7Sjsg 			       struct amdgpu_ih_ring *ih,
244fb4d8502Sjsg 			       struct amdgpu_iv_entry *entry)
245fb4d8502Sjsg {
246fb4d8502Sjsg 	/* wptr/rptr are in bytes! */
247c349dbc7Sjsg 	u32 ring_index = ih->rptr >> 2;
248fb4d8502Sjsg 	uint32_t dw[4];
249fb4d8502Sjsg 
250c349dbc7Sjsg 	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
251c349dbc7Sjsg 	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
252c349dbc7Sjsg 	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
253c349dbc7Sjsg 	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
254fb4d8502Sjsg 
255c349dbc7Sjsg 	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
256fb4d8502Sjsg 	entry->src_id = dw[0] & 0xff;
257fb4d8502Sjsg 	entry->src_data[0] = dw[1] & 0xfffffff;
258fb4d8502Sjsg 	entry->ring_id = dw[2] & 0xff;
259fb4d8502Sjsg 	entry->vmid = (dw[2] >> 8) & 0xff;
260fb4d8502Sjsg 	entry->pasid = (dw[2] >> 16) & 0xffff;
261fb4d8502Sjsg 
262fb4d8502Sjsg 	/* wptr/rptr are in bytes! */
263c349dbc7Sjsg 	ih->rptr += 16;
264fb4d8502Sjsg }
265fb4d8502Sjsg 
266fb4d8502Sjsg /**
267fb4d8502Sjsg  * tonga_ih_set_rptr - set the IH ring buffer rptr
268fb4d8502Sjsg  *
269fb4d8502Sjsg  * @adev: amdgpu_device pointer
2705ca02815Sjsg  * @ih: IH ring buffer to set rptr
271fb4d8502Sjsg  *
272fb4d8502Sjsg  * Set the IH ring buffer rptr.
273fb4d8502Sjsg  */
tonga_ih_set_rptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)274c349dbc7Sjsg static void tonga_ih_set_rptr(struct amdgpu_device *adev,
275c349dbc7Sjsg 			      struct amdgpu_ih_ring *ih)
276fb4d8502Sjsg {
277c349dbc7Sjsg 	if (ih->use_doorbell) {
278fb4d8502Sjsg 		/* XXX check if swapping is necessary on BE */
279c349dbc7Sjsg 		*ih->rptr_cpu = ih->rptr;
280c349dbc7Sjsg 		WDOORBELL32(ih->doorbell_index, ih->rptr);
281fb4d8502Sjsg 	} else {
282c349dbc7Sjsg 		WREG32(mmIH_RB_RPTR, ih->rptr);
283fb4d8502Sjsg 	}
284fb4d8502Sjsg }
285fb4d8502Sjsg 
tonga_ih_early_init(void * handle)286fb4d8502Sjsg static int tonga_ih_early_init(void *handle)
287fb4d8502Sjsg {
288fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
289fb4d8502Sjsg 	int ret;
290fb4d8502Sjsg 
291fb4d8502Sjsg 	ret = amdgpu_irq_add_domain(adev);
292fb4d8502Sjsg 	if (ret)
293fb4d8502Sjsg 		return ret;
294fb4d8502Sjsg 
295fb4d8502Sjsg 	tonga_ih_set_interrupt_funcs(adev);
296fb4d8502Sjsg 
297fb4d8502Sjsg 	return 0;
298fb4d8502Sjsg }
299fb4d8502Sjsg 
tonga_ih_sw_init(void * handle)300fb4d8502Sjsg static int tonga_ih_sw_init(void *handle)
301fb4d8502Sjsg {
302fb4d8502Sjsg 	int r;
303fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
304fb4d8502Sjsg 
305c349dbc7Sjsg 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
306fb4d8502Sjsg 	if (r)
307fb4d8502Sjsg 		return r;
308fb4d8502Sjsg 
309fb4d8502Sjsg 	adev->irq.ih.use_doorbell = true;
310c349dbc7Sjsg 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih;
311fb4d8502Sjsg 
312fb4d8502Sjsg 	r = amdgpu_irq_init(adev);
313fb4d8502Sjsg 
314fb4d8502Sjsg 	return r;
315fb4d8502Sjsg }
316fb4d8502Sjsg 
tonga_ih_sw_fini(void * handle)317fb4d8502Sjsg static int tonga_ih_sw_fini(void *handle)
318fb4d8502Sjsg {
319fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
320fb4d8502Sjsg 
3215ca02815Sjsg 	amdgpu_irq_fini_sw(adev);
322fb4d8502Sjsg 	amdgpu_irq_remove_domain(adev);
323fb4d8502Sjsg 
324fb4d8502Sjsg 	return 0;
325fb4d8502Sjsg }
326fb4d8502Sjsg 
tonga_ih_hw_init(void * handle)327fb4d8502Sjsg static int tonga_ih_hw_init(void *handle)
328fb4d8502Sjsg {
329fb4d8502Sjsg 	int r;
330fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
331fb4d8502Sjsg 
332fb4d8502Sjsg 	r = tonga_ih_irq_init(adev);
333fb4d8502Sjsg 	if (r)
334fb4d8502Sjsg 		return r;
335fb4d8502Sjsg 
336fb4d8502Sjsg 	return 0;
337fb4d8502Sjsg }
338fb4d8502Sjsg 
tonga_ih_hw_fini(void * handle)339fb4d8502Sjsg static int tonga_ih_hw_fini(void *handle)
340fb4d8502Sjsg {
341fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
342fb4d8502Sjsg 
343fb4d8502Sjsg 	tonga_ih_irq_disable(adev);
344fb4d8502Sjsg 
345fb4d8502Sjsg 	return 0;
346fb4d8502Sjsg }
347fb4d8502Sjsg 
tonga_ih_suspend(void * handle)348fb4d8502Sjsg static int tonga_ih_suspend(void *handle)
349fb4d8502Sjsg {
350fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
351fb4d8502Sjsg 
352fb4d8502Sjsg 	return tonga_ih_hw_fini(adev);
353fb4d8502Sjsg }
354fb4d8502Sjsg 
tonga_ih_resume(void * handle)355fb4d8502Sjsg static int tonga_ih_resume(void *handle)
356fb4d8502Sjsg {
357fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
358fb4d8502Sjsg 
359fb4d8502Sjsg 	return tonga_ih_hw_init(adev);
360fb4d8502Sjsg }
361fb4d8502Sjsg 
tonga_ih_is_idle(void * handle)362fb4d8502Sjsg static bool tonga_ih_is_idle(void *handle)
363fb4d8502Sjsg {
364fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
365fb4d8502Sjsg 	u32 tmp = RREG32(mmSRBM_STATUS);
366fb4d8502Sjsg 
367fb4d8502Sjsg 	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
368fb4d8502Sjsg 		return false;
369fb4d8502Sjsg 
370fb4d8502Sjsg 	return true;
371fb4d8502Sjsg }
372fb4d8502Sjsg 
tonga_ih_wait_for_idle(void * handle)373fb4d8502Sjsg static int tonga_ih_wait_for_idle(void *handle)
374fb4d8502Sjsg {
375fb4d8502Sjsg 	unsigned i;
376fb4d8502Sjsg 	u32 tmp;
377fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
378fb4d8502Sjsg 
379fb4d8502Sjsg 	for (i = 0; i < adev->usec_timeout; i++) {
380fb4d8502Sjsg 		/* read MC_STATUS */
381fb4d8502Sjsg 		tmp = RREG32(mmSRBM_STATUS);
382fb4d8502Sjsg 		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
383fb4d8502Sjsg 			return 0;
384fb4d8502Sjsg 		udelay(1);
385fb4d8502Sjsg 	}
386fb4d8502Sjsg 	return -ETIMEDOUT;
387fb4d8502Sjsg }
388fb4d8502Sjsg 
tonga_ih_check_soft_reset(void * handle)389fb4d8502Sjsg static bool tonga_ih_check_soft_reset(void *handle)
390fb4d8502Sjsg {
391fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
392fb4d8502Sjsg 	u32 srbm_soft_reset = 0;
393fb4d8502Sjsg 	u32 tmp = RREG32(mmSRBM_STATUS);
394fb4d8502Sjsg 
395fb4d8502Sjsg 	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
396fb4d8502Sjsg 		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
397fb4d8502Sjsg 						SOFT_RESET_IH, 1);
398fb4d8502Sjsg 
399fb4d8502Sjsg 	if (srbm_soft_reset) {
400fb4d8502Sjsg 		adev->irq.srbm_soft_reset = srbm_soft_reset;
401fb4d8502Sjsg 		return true;
402fb4d8502Sjsg 	} else {
403fb4d8502Sjsg 		adev->irq.srbm_soft_reset = 0;
404fb4d8502Sjsg 		return false;
405fb4d8502Sjsg 	}
406fb4d8502Sjsg }
407fb4d8502Sjsg 
tonga_ih_pre_soft_reset(void * handle)408fb4d8502Sjsg static int tonga_ih_pre_soft_reset(void *handle)
409fb4d8502Sjsg {
410fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
411fb4d8502Sjsg 
412fb4d8502Sjsg 	if (!adev->irq.srbm_soft_reset)
413fb4d8502Sjsg 		return 0;
414fb4d8502Sjsg 
415fb4d8502Sjsg 	return tonga_ih_hw_fini(adev);
416fb4d8502Sjsg }
417fb4d8502Sjsg 
tonga_ih_post_soft_reset(void * handle)418fb4d8502Sjsg static int tonga_ih_post_soft_reset(void *handle)
419fb4d8502Sjsg {
420fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
421fb4d8502Sjsg 
422fb4d8502Sjsg 	if (!adev->irq.srbm_soft_reset)
423fb4d8502Sjsg 		return 0;
424fb4d8502Sjsg 
425fb4d8502Sjsg 	return tonga_ih_hw_init(adev);
426fb4d8502Sjsg }
427fb4d8502Sjsg 
tonga_ih_soft_reset(void * handle)428fb4d8502Sjsg static int tonga_ih_soft_reset(void *handle)
429fb4d8502Sjsg {
430fb4d8502Sjsg 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
431fb4d8502Sjsg 	u32 srbm_soft_reset;
432fb4d8502Sjsg 
433fb4d8502Sjsg 	if (!adev->irq.srbm_soft_reset)
434fb4d8502Sjsg 		return 0;
435fb4d8502Sjsg 	srbm_soft_reset = adev->irq.srbm_soft_reset;
436fb4d8502Sjsg 
437fb4d8502Sjsg 	if (srbm_soft_reset) {
438fb4d8502Sjsg 		u32 tmp;
439fb4d8502Sjsg 
440fb4d8502Sjsg 		tmp = RREG32(mmSRBM_SOFT_RESET);
441fb4d8502Sjsg 		tmp |= srbm_soft_reset;
442fb4d8502Sjsg 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
443fb4d8502Sjsg 		WREG32(mmSRBM_SOFT_RESET, tmp);
444fb4d8502Sjsg 		tmp = RREG32(mmSRBM_SOFT_RESET);
445fb4d8502Sjsg 
446fb4d8502Sjsg 		udelay(50);
447fb4d8502Sjsg 
448fb4d8502Sjsg 		tmp &= ~srbm_soft_reset;
449fb4d8502Sjsg 		WREG32(mmSRBM_SOFT_RESET, tmp);
450fb4d8502Sjsg 		tmp = RREG32(mmSRBM_SOFT_RESET);
451fb4d8502Sjsg 
452fb4d8502Sjsg 		/* Wait a little for things to settle down */
453fb4d8502Sjsg 		udelay(50);
454fb4d8502Sjsg 	}
455fb4d8502Sjsg 
456fb4d8502Sjsg 	return 0;
457fb4d8502Sjsg }
458fb4d8502Sjsg 
tonga_ih_set_clockgating_state(void * handle,enum amd_clockgating_state state)459fb4d8502Sjsg static int tonga_ih_set_clockgating_state(void *handle,
460fb4d8502Sjsg 					  enum amd_clockgating_state state)
461fb4d8502Sjsg {
462fb4d8502Sjsg 	return 0;
463fb4d8502Sjsg }
464fb4d8502Sjsg 
tonga_ih_set_powergating_state(void * handle,enum amd_powergating_state state)465fb4d8502Sjsg static int tonga_ih_set_powergating_state(void *handle,
466fb4d8502Sjsg 					  enum amd_powergating_state state)
467fb4d8502Sjsg {
468fb4d8502Sjsg 	return 0;
469fb4d8502Sjsg }
470fb4d8502Sjsg 
471fb4d8502Sjsg static const struct amd_ip_funcs tonga_ih_ip_funcs = {
472fb4d8502Sjsg 	.name = "tonga_ih",
473fb4d8502Sjsg 	.early_init = tonga_ih_early_init,
474fb4d8502Sjsg 	.late_init = NULL,
475fb4d8502Sjsg 	.sw_init = tonga_ih_sw_init,
476fb4d8502Sjsg 	.sw_fini = tonga_ih_sw_fini,
477fb4d8502Sjsg 	.hw_init = tonga_ih_hw_init,
478fb4d8502Sjsg 	.hw_fini = tonga_ih_hw_fini,
479fb4d8502Sjsg 	.suspend = tonga_ih_suspend,
480fb4d8502Sjsg 	.resume = tonga_ih_resume,
481fb4d8502Sjsg 	.is_idle = tonga_ih_is_idle,
482fb4d8502Sjsg 	.wait_for_idle = tonga_ih_wait_for_idle,
483fb4d8502Sjsg 	.check_soft_reset = tonga_ih_check_soft_reset,
484fb4d8502Sjsg 	.pre_soft_reset = tonga_ih_pre_soft_reset,
485fb4d8502Sjsg 	.soft_reset = tonga_ih_soft_reset,
486fb4d8502Sjsg 	.post_soft_reset = tonga_ih_post_soft_reset,
487fb4d8502Sjsg 	.set_clockgating_state = tonga_ih_set_clockgating_state,
488fb4d8502Sjsg 	.set_powergating_state = tonga_ih_set_powergating_state,
489fb4d8502Sjsg };
490fb4d8502Sjsg 
491fb4d8502Sjsg static const struct amdgpu_ih_funcs tonga_ih_funcs = {
492fb4d8502Sjsg 	.get_wptr = tonga_ih_get_wptr,
493fb4d8502Sjsg 	.decode_iv = tonga_ih_decode_iv,
494fb4d8502Sjsg 	.set_rptr = tonga_ih_set_rptr
495fb4d8502Sjsg };
496fb4d8502Sjsg 
tonga_ih_set_interrupt_funcs(struct amdgpu_device * adev)497fb4d8502Sjsg static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
498fb4d8502Sjsg {
499fb4d8502Sjsg 	adev->irq.ih_funcs = &tonga_ih_funcs;
500fb4d8502Sjsg }
501fb4d8502Sjsg 
502f005ef32Sjsg const struct amdgpu_ip_block_version tonga_ih_ip_block = {
503fb4d8502Sjsg 	.type = AMD_IP_BLOCK_TYPE_IH,
504fb4d8502Sjsg 	.major = 3,
505fb4d8502Sjsg 	.minor = 0,
506fb4d8502Sjsg 	.rev = 0,
507fb4d8502Sjsg 	.funcs = &tonga_ih_ip_funcs,
508fb4d8502Sjsg };
509