1*1bb76ff1Sjsg /* SPDX-License-Identifier: MIT
2*1bb76ff1Sjsg * Copyright 2021 Advanced Micro Devices, Inc.
3*1bb76ff1Sjsg *
4*1bb76ff1Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5*1bb76ff1Sjsg * copy of this software and associated documentation files (the "Software"),
6*1bb76ff1Sjsg * to deal in the Software without restriction, including without limitation
7*1bb76ff1Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*1bb76ff1Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9*1bb76ff1Sjsg * Software is furnished to do so, subject to the following conditions:
10*1bb76ff1Sjsg *
11*1bb76ff1Sjsg * The above copyright notice and this permission notice shall be included in
12*1bb76ff1Sjsg * all copies or substantial portions of the Software.
13*1bb76ff1Sjsg *
14*1bb76ff1Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*1bb76ff1Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*1bb76ff1Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*1bb76ff1Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*1bb76ff1Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*1bb76ff1Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*1bb76ff1Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21*1bb76ff1Sjsg *
22*1bb76ff1Sjsg */
23*1bb76ff1Sjsg
24*1bb76ff1Sjsg #ifndef __AMDGPU_VRAM_MGR_H__
25*1bb76ff1Sjsg #define __AMDGPU_VRAM_MGR_H__
26*1bb76ff1Sjsg
27*1bb76ff1Sjsg #include <drm/drm_buddy.h>
28*1bb76ff1Sjsg
29*1bb76ff1Sjsg struct amdgpu_vram_mgr {
30*1bb76ff1Sjsg struct ttm_resource_manager manager;
31*1bb76ff1Sjsg struct drm_buddy mm;
32*1bb76ff1Sjsg /* protects access to buffer objects */
33*1bb76ff1Sjsg struct rwlock lock;
34*1bb76ff1Sjsg struct list_head reservations_pending;
35*1bb76ff1Sjsg struct list_head reserved_pages;
36*1bb76ff1Sjsg atomic64_t vis_usage;
37*1bb76ff1Sjsg u64 default_page_size;
38*1bb76ff1Sjsg };
39*1bb76ff1Sjsg
40*1bb76ff1Sjsg struct amdgpu_vram_mgr_resource {
41*1bb76ff1Sjsg struct ttm_resource base;
42*1bb76ff1Sjsg struct list_head blocks;
43*1bb76ff1Sjsg unsigned long flags;
44*1bb76ff1Sjsg };
45*1bb76ff1Sjsg
amdgpu_vram_mgr_block_start(struct drm_buddy_block * block)46*1bb76ff1Sjsg static inline u64 amdgpu_vram_mgr_block_start(struct drm_buddy_block *block)
47*1bb76ff1Sjsg {
48*1bb76ff1Sjsg return drm_buddy_block_offset(block);
49*1bb76ff1Sjsg }
50*1bb76ff1Sjsg
amdgpu_vram_mgr_block_size(struct drm_buddy_block * block)51*1bb76ff1Sjsg static inline u64 amdgpu_vram_mgr_block_size(struct drm_buddy_block *block)
52*1bb76ff1Sjsg {
53*1bb76ff1Sjsg return (u64)PAGE_SIZE << drm_buddy_block_order(block);
54*1bb76ff1Sjsg }
55*1bb76ff1Sjsg
56*1bb76ff1Sjsg static inline struct amdgpu_vram_mgr_resource *
to_amdgpu_vram_mgr_resource(struct ttm_resource * res)57*1bb76ff1Sjsg to_amdgpu_vram_mgr_resource(struct ttm_resource *res)
58*1bb76ff1Sjsg {
59*1bb76ff1Sjsg return container_of(res, struct amdgpu_vram_mgr_resource, base);
60*1bb76ff1Sjsg }
61*1bb76ff1Sjsg
62*1bb76ff1Sjsg #endif
63