1c349dbc7Sjsg /*
2c349dbc7Sjsg * Copyright 2019 Advanced Micro Devices, Inc.
3c349dbc7Sjsg *
4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"),
6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation
7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions:
10c349dbc7Sjsg *
11c349dbc7Sjsg * The above copyright notice and this permission notice shall be included in
12c349dbc7Sjsg * all copies or substantial portions of the Software.
13c349dbc7Sjsg *
14c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18c349dbc7Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19c349dbc7Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20c349dbc7Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21c349dbc7Sjsg */
22c349dbc7Sjsg
23c349dbc7Sjsg #include "amdgpu_vm.h"
24c349dbc7Sjsg #include "amdgpu_object.h"
25c349dbc7Sjsg #include "amdgpu_trace.h"
26c349dbc7Sjsg
27c349dbc7Sjsg /**
28c349dbc7Sjsg * amdgpu_vm_cpu_map_table - make sure new PDs/PTs are kmapped
29c349dbc7Sjsg *
30c349dbc7Sjsg * @table: newly allocated or validated PD/PT
31c349dbc7Sjsg */
amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm * table)325ca02815Sjsg static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table)
33c349dbc7Sjsg {
34*f005ef32Sjsg table->bo.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
355ca02815Sjsg return amdgpu_bo_kmap(&table->bo, NULL);
36c349dbc7Sjsg }
37c349dbc7Sjsg
38c349dbc7Sjsg /**
39c349dbc7Sjsg * amdgpu_vm_cpu_prepare - prepare page table update with the CPU
40c349dbc7Sjsg *
41c349dbc7Sjsg * @p: see amdgpu_vm_update_params definition
425ca02815Sjsg * @resv: reservation object with embedded fence
435ca02815Sjsg * @sync_mode: synchronization mode
44c349dbc7Sjsg *
45c349dbc7Sjsg * Returns:
46c349dbc7Sjsg * Negativ errno, 0 for success.
47c349dbc7Sjsg */
amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params * p,struct dma_resv * resv,enum amdgpu_sync_mode sync_mode)48c349dbc7Sjsg static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,
49c349dbc7Sjsg struct dma_resv *resv,
50c349dbc7Sjsg enum amdgpu_sync_mode sync_mode)
51c349dbc7Sjsg {
52c349dbc7Sjsg if (!resv)
53c349dbc7Sjsg return 0;
54c349dbc7Sjsg
55c349dbc7Sjsg return amdgpu_bo_sync_wait_resv(p->adev, resv, sync_mode, p->vm, true);
56c349dbc7Sjsg }
57c349dbc7Sjsg
58c349dbc7Sjsg /**
59c349dbc7Sjsg * amdgpu_vm_cpu_update - helper to update page tables via CPU
60c349dbc7Sjsg *
61c349dbc7Sjsg * @p: see amdgpu_vm_update_params definition
625ca02815Sjsg * @vmbo: PD/PT to update
63ad8b1aafSjsg * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
64c349dbc7Sjsg * @addr: dst addr to write into pe
65c349dbc7Sjsg * @count: number of page entries to update
66c349dbc7Sjsg * @incr: increase next addr by incr bytes
67c349dbc7Sjsg * @flags: hw access flags
68c349dbc7Sjsg *
69c349dbc7Sjsg * Write count number of PT/PD entries directly.
70c349dbc7Sjsg */
amdgpu_vm_cpu_update(struct amdgpu_vm_update_params * p,struct amdgpu_bo_vm * vmbo,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)71c349dbc7Sjsg static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,
725ca02815Sjsg struct amdgpu_bo_vm *vmbo, uint64_t pe,
73c349dbc7Sjsg uint64_t addr, unsigned count, uint32_t incr,
74c349dbc7Sjsg uint64_t flags)
75c349dbc7Sjsg {
76c349dbc7Sjsg unsigned int i;
77c349dbc7Sjsg uint64_t value;
781bb76ff1Sjsg long r;
79c349dbc7Sjsg
801bb76ff1Sjsg r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL,
811bb76ff1Sjsg true, MAX_SCHEDULE_TIMEOUT);
821bb76ff1Sjsg if (r < 0)
83c349dbc7Sjsg return r;
84c349dbc7Sjsg
855ca02815Sjsg pe += (unsigned long)amdgpu_bo_kptr(&vmbo->bo);
86c349dbc7Sjsg
87ad8b1aafSjsg trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);
88c349dbc7Sjsg
89c349dbc7Sjsg for (i = 0; i < count; i++) {
90c349dbc7Sjsg value = p->pages_addr ?
91c349dbc7Sjsg amdgpu_vm_map_gart(p->pages_addr, addr) :
92c349dbc7Sjsg addr;
93c349dbc7Sjsg amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe,
94c349dbc7Sjsg i, value, flags);
95c349dbc7Sjsg addr += incr;
96c349dbc7Sjsg }
97c349dbc7Sjsg return 0;
98c349dbc7Sjsg }
99c349dbc7Sjsg
100c349dbc7Sjsg /**
101c349dbc7Sjsg * amdgpu_vm_cpu_commit - commit page table update to the HW
102c349dbc7Sjsg *
103c349dbc7Sjsg * @p: see amdgpu_vm_update_params definition
104c349dbc7Sjsg * @fence: unused
105c349dbc7Sjsg *
106c349dbc7Sjsg * Make sure that the hardware sees the page table updates.
107c349dbc7Sjsg */
amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params * p,struct dma_fence ** fence)108c349dbc7Sjsg static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
109c349dbc7Sjsg struct dma_fence **fence)
110c349dbc7Sjsg {
111c349dbc7Sjsg /* Flush HDP */
112c349dbc7Sjsg mb();
1135ca02815Sjsg amdgpu_device_flush_hdp(p->adev, NULL);
114c349dbc7Sjsg return 0;
115c349dbc7Sjsg }
116c349dbc7Sjsg
117c349dbc7Sjsg const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs = {
118c349dbc7Sjsg .map_table = amdgpu_vm_cpu_map_table,
119c349dbc7Sjsg .prepare = amdgpu_vm_cpu_prepare,
120c349dbc7Sjsg .update = amdgpu_vm_cpu_update,
121c349dbc7Sjsg .commit = amdgpu_vm_cpu_commit
122c349dbc7Sjsg };
123