1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2016 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg * Author: Monk.liu@amd.com 23fb4d8502Sjsg */ 24fb4d8502Sjsg #ifndef AMDGPU_VIRT_H 25fb4d8502Sjsg #define AMDGPU_VIRT_H 26fb4d8502Sjsg 27ad8b1aafSjsg #include "amdgv_sriovmsg.h" 28ad8b1aafSjsg 29fb4d8502Sjsg #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30fb4d8502Sjsg #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31fb4d8502Sjsg #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32fb4d8502Sjsg #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33fb4d8502Sjsg #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 341bb76ff1Sjsg #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 351bb76ff1Sjsg 361bb76ff1Sjsg /* flags for indirect register access path supported by rlcg for sriov */ 371bb76ff1Sjsg #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 381bb76ff1Sjsg #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 391bb76ff1Sjsg #define AMDGPU_RLCG_GC_READ (0x1 << 28) 401bb76ff1Sjsg #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 411bb76ff1Sjsg 421bb76ff1Sjsg /* error code for indirect register access path supported by rlcg for sriov */ 431bb76ff1Sjsg #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 441bb76ff1Sjsg #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 451bb76ff1Sjsg #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 461bb76ff1Sjsg 471bb76ff1Sjsg #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48fb4d8502Sjsg 49ad8b1aafSjsg /* all asic after AI use this offset */ 50ad8b1aafSjsg #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 51ad8b1aafSjsg /* tonga/fiji use this offset */ 52ad8b1aafSjsg #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 53ad8b1aafSjsg 54ad8b1aafSjsg enum amdgpu_sriov_vf_mode { 55ad8b1aafSjsg SRIOV_VF_MODE_BARE_METAL = 0, 56ad8b1aafSjsg SRIOV_VF_MODE_ONE_VF, 57ad8b1aafSjsg SRIOV_VF_MODE_MULTI_VF, 58ad8b1aafSjsg }; 59ad8b1aafSjsg 60fb4d8502Sjsg struct amdgpu_mm_table { 61fb4d8502Sjsg struct amdgpu_bo *bo; 62fb4d8502Sjsg uint32_t *cpu_addr; 63fb4d8502Sjsg uint64_t gpu_addr; 64fb4d8502Sjsg }; 65fb4d8502Sjsg 66fb4d8502Sjsg #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 67fb4d8502Sjsg 68fb4d8502Sjsg /* struct error_entry - amdgpu VF error information. */ 69fb4d8502Sjsg struct amdgpu_vf_error_buffer { 70fb4d8502Sjsg struct rwlock lock; 71fb4d8502Sjsg int read_count; 72fb4d8502Sjsg int write_count; 73fb4d8502Sjsg uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 74fb4d8502Sjsg uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 75fb4d8502Sjsg uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 76fb4d8502Sjsg }; 77fb4d8502Sjsg 781bb76ff1Sjsg enum idh_request; 791bb76ff1Sjsg 80fb4d8502Sjsg /** 81fb4d8502Sjsg * struct amdgpu_virt_ops - amdgpu device virt operations 82fb4d8502Sjsg */ 83fb4d8502Sjsg struct amdgpu_virt_ops { 84fb4d8502Sjsg int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 85fb4d8502Sjsg int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 86ad8b1aafSjsg int (*req_init_data)(struct amdgpu_device *adev); 87fb4d8502Sjsg int (*reset_gpu)(struct amdgpu_device *adev); 88fb4d8502Sjsg int (*wait_reset)(struct amdgpu_device *adev); 891bb76ff1Sjsg void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 901bb76ff1Sjsg u32 data1, u32 data2, u32 data3); 91f005ef32Sjsg void (*ras_poison_handler)(struct amdgpu_device *adev); 92fb4d8502Sjsg }; 93fb4d8502Sjsg 94fb4d8502Sjsg /* 95fb4d8502Sjsg * Firmware Reserve Frame buffer 96fb4d8502Sjsg */ 97fb4d8502Sjsg struct amdgpu_virt_fw_reserve { 98c349dbc7Sjsg struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 99c349dbc7Sjsg struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 100fb4d8502Sjsg unsigned int checksum_key; 101fb4d8502Sjsg }; 102ad8b1aafSjsg 103fb4d8502Sjsg /* 104ad8b1aafSjsg * Legacy GIM header 105ad8b1aafSjsg * 106fb4d8502Sjsg * Defination between PF and VF 107fb4d8502Sjsg * Structures forcibly aligned to 4 to keep the same style as PF. 108fb4d8502Sjsg */ 109fb4d8502Sjsg #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 110fb4d8502Sjsg 111fb4d8502Sjsg #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 112fb4d8502Sjsg (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 113fb4d8502Sjsg 114fb4d8502Sjsg enum AMDGIM_FEATURE_FLAG { 115fb4d8502Sjsg /* GIM supports feature of Error log collecting */ 116fb4d8502Sjsg AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 117fb4d8502Sjsg /* GIM supports feature of loading uCodes */ 118fb4d8502Sjsg AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 119fb4d8502Sjsg /* VRAM LOST by GIM */ 120fb4d8502Sjsg AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 121ad8b1aafSjsg /* MM bandwidth */ 122ad8b1aafSjsg AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 123c349dbc7Sjsg /* PP ONE VF MODE in GIM */ 124c349dbc7Sjsg AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 1255ca02815Sjsg /* Indirect Reg Access enabled */ 1265ca02815Sjsg AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 127f005ef32Sjsg /* AV1 Support MODE*/ 128f005ef32Sjsg AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6), 1295ca02815Sjsg }; 1305ca02815Sjsg 1315ca02815Sjsg enum AMDGIM_REG_ACCESS_FLAG { 1325ca02815Sjsg /* Use PSP to program IH_RB_CNTL */ 1335ca02815Sjsg AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 1345ca02815Sjsg /* Use RLC to program MMHUB regs */ 1355ca02815Sjsg AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 1365ca02815Sjsg /* Use RLC to program GC regs */ 1375ca02815Sjsg AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 138fb4d8502Sjsg }; 139fb4d8502Sjsg 140fb4d8502Sjsg struct amdgim_pf2vf_info_v1 { 141fb4d8502Sjsg /* header contains size and version */ 142c349dbc7Sjsg struct amd_sriov_msg_pf2vf_info_header header; 143fb4d8502Sjsg /* max_width * max_height */ 144fb4d8502Sjsg unsigned int uvd_enc_max_pixels_count; 145fb4d8502Sjsg /* 16x16 pixels/sec, codec independent */ 146fb4d8502Sjsg unsigned int uvd_enc_max_bandwidth; 147fb4d8502Sjsg /* max_width * max_height */ 148fb4d8502Sjsg unsigned int vce_enc_max_pixels_count; 149fb4d8502Sjsg /* 16x16 pixels/sec, codec independent */ 150fb4d8502Sjsg unsigned int vce_enc_max_bandwidth; 151fb4d8502Sjsg /* MEC FW position in kb from the start of visible frame buffer */ 152fb4d8502Sjsg unsigned int mecfw_kboffset; 153fb4d8502Sjsg /* The features flags of the GIM driver supports. */ 154fb4d8502Sjsg unsigned int feature_flags; 155fb4d8502Sjsg /* use private key from mailbox 2 to create chueksum */ 156fb4d8502Sjsg unsigned int checksum; 157fb4d8502Sjsg } __aligned(4); 158fb4d8502Sjsg 159fb4d8502Sjsg struct amdgim_vf2pf_info_v1 { 160fb4d8502Sjsg /* header contains size and version */ 161c349dbc7Sjsg struct amd_sriov_msg_vf2pf_info_header header; 162fb4d8502Sjsg /* driver version */ 163fb4d8502Sjsg char driver_version[64]; 164fb4d8502Sjsg /* driver certification, 1=WHQL, 0=None */ 165fb4d8502Sjsg unsigned int driver_cert; 166fb4d8502Sjsg /* guest OS type and version: need a define */ 167fb4d8502Sjsg unsigned int os_info; 168fb4d8502Sjsg /* in the unit of 1M */ 169fb4d8502Sjsg unsigned int fb_usage; 170fb4d8502Sjsg /* guest gfx engine usage percentage */ 171fb4d8502Sjsg unsigned int gfx_usage; 172fb4d8502Sjsg /* guest gfx engine health percentage */ 173fb4d8502Sjsg unsigned int gfx_health; 174fb4d8502Sjsg /* guest compute engine usage percentage */ 175fb4d8502Sjsg unsigned int compute_usage; 176fb4d8502Sjsg /* guest compute engine health percentage */ 177fb4d8502Sjsg unsigned int compute_health; 178fb4d8502Sjsg /* guest vce engine usage percentage. 0xffff means N/A. */ 179fb4d8502Sjsg unsigned int vce_enc_usage; 180fb4d8502Sjsg /* guest vce engine health percentage. 0xffff means N/A. */ 181fb4d8502Sjsg unsigned int vce_enc_health; 182fb4d8502Sjsg /* guest uvd engine usage percentage. 0xffff means N/A. */ 183fb4d8502Sjsg unsigned int uvd_enc_usage; 184fb4d8502Sjsg /* guest uvd engine usage percentage. 0xffff means N/A. */ 185fb4d8502Sjsg unsigned int uvd_enc_health; 186fb4d8502Sjsg unsigned int checksum; 187fb4d8502Sjsg } __aligned(4); 188fb4d8502Sjsg 189fb4d8502Sjsg struct amdgim_vf2pf_info_v2 { 190fb4d8502Sjsg /* header contains size and version */ 191c349dbc7Sjsg struct amd_sriov_msg_vf2pf_info_header header; 192fb4d8502Sjsg uint32_t checksum; 193fb4d8502Sjsg /* driver version */ 194fb4d8502Sjsg uint8_t driver_version[64]; 195fb4d8502Sjsg /* driver certification, 1=WHQL, 0=None */ 196fb4d8502Sjsg uint32_t driver_cert; 197fb4d8502Sjsg /* guest OS type and version: need a define */ 198fb4d8502Sjsg uint32_t os_info; 199fb4d8502Sjsg /* in the unit of 1M */ 200fb4d8502Sjsg uint32_t fb_usage; 201fb4d8502Sjsg /* guest gfx engine usage percentage */ 202fb4d8502Sjsg uint32_t gfx_usage; 203fb4d8502Sjsg /* guest gfx engine health percentage */ 204fb4d8502Sjsg uint32_t gfx_health; 205fb4d8502Sjsg /* guest compute engine usage percentage */ 206fb4d8502Sjsg uint32_t compute_usage; 207fb4d8502Sjsg /* guest compute engine health percentage */ 208fb4d8502Sjsg uint32_t compute_health; 209fb4d8502Sjsg /* guest vce engine usage percentage. 0xffff means N/A. */ 210fb4d8502Sjsg uint32_t vce_enc_usage; 211fb4d8502Sjsg /* guest vce engine health percentage. 0xffff means N/A. */ 212fb4d8502Sjsg uint32_t vce_enc_health; 213fb4d8502Sjsg /* guest uvd engine usage percentage. 0xffff means N/A. */ 214fb4d8502Sjsg uint32_t uvd_enc_usage; 215fb4d8502Sjsg /* guest uvd engine usage percentage. 0xffff means N/A. */ 216fb4d8502Sjsg uint32_t uvd_enc_health; 217c349dbc7Sjsg uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 218fb4d8502Sjsg } __aligned(4); 219fb4d8502Sjsg 220ad8b1aafSjsg struct amdgpu_virt_ras_err_handler_data { 221ad8b1aafSjsg /* point to bad page records array */ 222ad8b1aafSjsg struct eeprom_table_record *bps; 223ad8b1aafSjsg /* point to reserved bo array */ 224ad8b1aafSjsg struct amdgpu_bo **bps_bo; 225ad8b1aafSjsg /* the count of entries */ 226ad8b1aafSjsg int count; 227ad8b1aafSjsg /* last reserved entry's index + 1 */ 228ad8b1aafSjsg int last_reserved; 229ad8b1aafSjsg }; 230fb4d8502Sjsg 231fb4d8502Sjsg /* GPU virtualization */ 232fb4d8502Sjsg struct amdgpu_virt { 233fb4d8502Sjsg uint32_t caps; 234fb4d8502Sjsg struct amdgpu_bo *csa_obj; 235c349dbc7Sjsg void *csa_cpu_addr; 236fb4d8502Sjsg bool chained_ib_support; 237fb4d8502Sjsg uint32_t reg_val_offs; 238fb4d8502Sjsg struct amdgpu_irq_src ack_irq; 239fb4d8502Sjsg struct amdgpu_irq_src rcv_irq; 240fb4d8502Sjsg struct work_struct flr_work; 241fb4d8502Sjsg struct amdgpu_mm_table mm_table; 242fb4d8502Sjsg const struct amdgpu_virt_ops *ops; 243fb4d8502Sjsg struct amdgpu_vf_error_buffer vf_errors; 244fb4d8502Sjsg struct amdgpu_virt_fw_reserve fw_reserve; 245fb4d8502Sjsg uint32_t gim_feature; 246c349dbc7Sjsg uint32_t reg_access_mode; 247ad8b1aafSjsg int req_init_data_ver; 248ad8b1aafSjsg bool tdr_debug; 249ad8b1aafSjsg struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 250ad8b1aafSjsg bool ras_init_done; 2515ca02815Sjsg uint32_t reg_access; 252ad8b1aafSjsg 253ad8b1aafSjsg /* vf2pf message */ 254ad8b1aafSjsg struct delayed_work vf2pf_work; 255ad8b1aafSjsg uint32_t vf2pf_update_interval_ms; 2565ca02815Sjsg 2575ca02815Sjsg /* multimedia bandwidth config */ 2585ca02815Sjsg bool is_mm_bw_enabled; 2595ca02815Sjsg uint32_t decode_max_dimension_pixels; 2605ca02815Sjsg uint32_t decode_max_frame_pixels; 2615ca02815Sjsg uint32_t encode_max_dimension_pixels; 2625ca02815Sjsg uint32_t encode_max_frame_pixels; 2631bb76ff1Sjsg 2641bb76ff1Sjsg /* the ucode id to signal the autoload */ 2651bb76ff1Sjsg uint32_t autoload_ucode_id; 266*6f63516cSjsg 267*6f63516cSjsg struct rwlock rlcg_reg_lock; 268fb4d8502Sjsg }; 269fb4d8502Sjsg 2705ca02815Sjsg struct amdgpu_video_codec_info; 2715ca02815Sjsg 272fb4d8502Sjsg #define amdgpu_sriov_enabled(adev) \ 273fb4d8502Sjsg ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 274fb4d8502Sjsg 275fb4d8502Sjsg #define amdgpu_sriov_vf(adev) \ 276fb4d8502Sjsg ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 277fb4d8502Sjsg 278fb4d8502Sjsg #define amdgpu_sriov_bios(adev) \ 279fb4d8502Sjsg ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 280fb4d8502Sjsg 281fb4d8502Sjsg #define amdgpu_sriov_runtime(adev) \ 282fb4d8502Sjsg ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 283fb4d8502Sjsg 284c349dbc7Sjsg #define amdgpu_sriov_fullaccess(adev) \ 285c349dbc7Sjsg (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 286c349dbc7Sjsg 2875ca02815Sjsg #define amdgpu_sriov_reg_indirect_en(adev) \ 2885ca02815Sjsg (amdgpu_sriov_vf((adev)) && \ 2895ca02815Sjsg ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 2905ca02815Sjsg 2915ca02815Sjsg #define amdgpu_sriov_reg_indirect_ih(adev) \ 2925ca02815Sjsg (amdgpu_sriov_vf((adev)) && \ 2935ca02815Sjsg ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 2945ca02815Sjsg 2955ca02815Sjsg #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 2965ca02815Sjsg (amdgpu_sriov_vf((adev)) && \ 2975ca02815Sjsg ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 2985ca02815Sjsg 2995ca02815Sjsg #define amdgpu_sriov_reg_indirect_gc(adev) \ 3005ca02815Sjsg (amdgpu_sriov_vf((adev)) && \ 3015ca02815Sjsg ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 3025ca02815Sjsg 3031bb76ff1Sjsg #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 3041bb76ff1Sjsg (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 3051bb76ff1Sjsg 306fb4d8502Sjsg #define amdgpu_passthrough(adev) \ 307fb4d8502Sjsg ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 308fb4d8502Sjsg 3091bb76ff1Sjsg #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 3101bb76ff1Sjsg ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 3111bb76ff1Sjsg 312fb4d8502Sjsg static inline bool is_virtual_machine(void) 313fb4d8502Sjsg { 3141bb76ff1Sjsg #if defined(CONFIG_X86) 315fb4d8502Sjsg return boot_cpu_has(X86_FEATURE_HYPERVISOR); 3161bb76ff1Sjsg #elif defined(CONFIG_ARM64) && defined(notyet) 3171bb76ff1Sjsg return !is_kernel_in_hyp_mode(); 318fb4d8502Sjsg #else 319fb4d8502Sjsg return false; 320fb4d8502Sjsg #endif 321fb4d8502Sjsg } 322fb4d8502Sjsg 323c349dbc7Sjsg #define amdgpu_sriov_is_pp_one_vf(adev) \ 324c349dbc7Sjsg ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 325ad8b1aafSjsg #define amdgpu_sriov_is_debug(adev) \ 326ad8b1aafSjsg ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 327ad8b1aafSjsg #define amdgpu_sriov_is_normal(adev) \ 328ad8b1aafSjsg ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 329f005ef32Sjsg #define amdgpu_sriov_is_av1_support(adev) \ 330f005ef32Sjsg ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT) 331fb4d8502Sjsg bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 332fb4d8502Sjsg void amdgpu_virt_init_setting(struct amdgpu_device *adev); 333c349dbc7Sjsg void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 334c349dbc7Sjsg uint32_t reg0, uint32_t rreg1, 335c349dbc7Sjsg uint32_t ref, uint32_t mask); 336fb4d8502Sjsg int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 337fb4d8502Sjsg int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 338fb4d8502Sjsg int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 339ad8b1aafSjsg void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 340fb4d8502Sjsg int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 341fb4d8502Sjsg int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 342fb4d8502Sjsg void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 343ad8b1aafSjsg void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 344fb4d8502Sjsg void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 34515f9b5f9Sjsg void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 346ad8b1aafSjsg void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 347ad8b1aafSjsg void amdgpu_detect_virtualization(struct amdgpu_device *adev); 348ad8b1aafSjsg 349ad8b1aafSjsg bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 350ad8b1aafSjsg int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 351ad8b1aafSjsg void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 352ad8b1aafSjsg 353ad8b1aafSjsg enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 3545ca02815Sjsg 3555ca02815Sjsg void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 3565ca02815Sjsg struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 3575ca02815Sjsg struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 3581bb76ff1Sjsg void amdgpu_sriov_wreg(struct amdgpu_device *adev, 3591bb76ff1Sjsg u32 offset, u32 value, 360f005ef32Sjsg u32 acc_flags, u32 hwip, u32 xcc_id); 3611bb76ff1Sjsg u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 362f005ef32Sjsg u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 3631bb76ff1Sjsg bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 3641bb76ff1Sjsg uint32_t ucode_id); 365f005ef32Sjsg void amdgpu_virt_post_reset(struct amdgpu_device *adev); 366fb4d8502Sjsg #endif 367