11bb76ff1Sjsg /* 21bb76ff1Sjsg * Copyright 2021 Advanced Micro Devices, Inc. 31bb76ff1Sjsg * 41bb76ff1Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 51bb76ff1Sjsg * copy of this software and associated documentation files (the "Software"), 61bb76ff1Sjsg * to deal in the Software without restriction, including without limitation 71bb76ff1Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 81bb76ff1Sjsg * and/or sell copies of the Software, and to permit persons to whom the 91bb76ff1Sjsg * Software is furnished to do so, subject to the following conditions: 101bb76ff1Sjsg * 111bb76ff1Sjsg * The above copyright notice and this permission notice shall be included in 121bb76ff1Sjsg * all copies or substantial portions of the Software. 131bb76ff1Sjsg * 141bb76ff1Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 151bb76ff1Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 161bb76ff1Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 171bb76ff1Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 181bb76ff1Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 191bb76ff1Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 201bb76ff1Sjsg * OTHER DEALINGS IN THE SOFTWARE. 211bb76ff1Sjsg * 221bb76ff1Sjsg */ 231bb76ff1Sjsg #include <linux/ioctl.h> 241bb76ff1Sjsg 251bb76ff1Sjsg /* 261bb76ff1Sjsg * MMIO debugfs IOCTL structure 271bb76ff1Sjsg */ 281bb76ff1Sjsg struct amdgpu_debugfs_regs2_iocdata { 291bb76ff1Sjsg __u32 use_srbm, use_grbm, pg_lock; 301bb76ff1Sjsg struct { 311bb76ff1Sjsg __u32 se, sh, instance; 321bb76ff1Sjsg } grbm; 331bb76ff1Sjsg struct { 341bb76ff1Sjsg __u32 me, pipe, queue, vmid; 351bb76ff1Sjsg } srbm; 361bb76ff1Sjsg }; 371bb76ff1Sjsg 38*f005ef32Sjsg struct amdgpu_debugfs_regs2_iocdata_v2 { 39*f005ef32Sjsg __u32 use_srbm, use_grbm, pg_lock; 40*f005ef32Sjsg struct { 41*f005ef32Sjsg __u32 se, sh, instance; 42*f005ef32Sjsg } grbm; 43*f005ef32Sjsg struct { 44*f005ef32Sjsg __u32 me, pipe, queue, vmid; 45*f005ef32Sjsg } srbm; 46*f005ef32Sjsg u32 xcc_id; 47*f005ef32Sjsg }; 48*f005ef32Sjsg 49*f005ef32Sjsg struct amdgpu_debugfs_gprwave_iocdata { 50*f005ef32Sjsg u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; 51*f005ef32Sjsg struct { 52*f005ef32Sjsg u32 thread, vpgr_or_sgpr; 53*f005ef32Sjsg } gpr; 54*f005ef32Sjsg }; 55*f005ef32Sjsg 561bb76ff1Sjsg /* 571bb76ff1Sjsg * MMIO debugfs state data (per file* handle) 581bb76ff1Sjsg */ 591bb76ff1Sjsg struct amdgpu_debugfs_regs2_data { 601bb76ff1Sjsg struct amdgpu_device *adev; 611bb76ff1Sjsg struct mutex lock; 62*f005ef32Sjsg struct amdgpu_debugfs_regs2_iocdata_v2 id; 63*f005ef32Sjsg }; 64*f005ef32Sjsg 65*f005ef32Sjsg struct amdgpu_debugfs_gprwave_data { 66*f005ef32Sjsg struct amdgpu_device *adev; 67*f005ef32Sjsg struct mutex lock; 68*f005ef32Sjsg struct amdgpu_debugfs_gprwave_iocdata id; 691bb76ff1Sjsg }; 701bb76ff1Sjsg 711bb76ff1Sjsg enum AMDGPU_DEBUGFS_REGS2_CMDS { 721bb76ff1Sjsg AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE=0, 73*f005ef32Sjsg AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2, 741bb76ff1Sjsg }; 751bb76ff1Sjsg 76*f005ef32Sjsg enum AMDGPU_DEBUGFS_GPRWAVE_CMDS { 77*f005ef32Sjsg AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE=0, 78*f005ef32Sjsg }; 79*f005ef32Sjsg 80*f005ef32Sjsg //reg2 interface 811bb76ff1Sjsg #define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE, struct amdgpu_debugfs_regs2_iocdata) 82*f005ef32Sjsg #define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2 _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2, struct amdgpu_debugfs_regs2_iocdata_v2) 83*f005ef32Sjsg 84*f005ef32Sjsg //gprwave interface 85*f005ef32Sjsg #define AMDGPU_DEBUGFS_GPRWAVE_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE, struct amdgpu_debugfs_gprwave_iocdata) 86