1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2016 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg * Authors: Christian König 23fb4d8502Sjsg */ 24fb4d8502Sjsg #ifndef __AMDGPU_SYNC_H__ 25fb4d8502Sjsg #define __AMDGPU_SYNC_H__ 26fb4d8502Sjsg 27fb4d8502Sjsg #include <linux/hashtable.h> 28fb4d8502Sjsg 29fb4d8502Sjsg struct dma_fence; 30c349dbc7Sjsg struct dma_resv; 31fb4d8502Sjsg struct amdgpu_device; 32fb4d8502Sjsg struct amdgpu_ring; 33*f005ef32Sjsg struct amdgpu_job; 34fb4d8502Sjsg 35c349dbc7Sjsg enum amdgpu_sync_mode { 36c349dbc7Sjsg AMDGPU_SYNC_ALWAYS, 37c349dbc7Sjsg AMDGPU_SYNC_NE_OWNER, 38c349dbc7Sjsg AMDGPU_SYNC_EQ_OWNER, 39c349dbc7Sjsg AMDGPU_SYNC_EXPLICIT 40c349dbc7Sjsg }; 41c349dbc7Sjsg 42fb4d8502Sjsg /* 43fb4d8502Sjsg * Container for fences used to sync command submissions. 44fb4d8502Sjsg */ 45fb4d8502Sjsg struct amdgpu_sync { 46fb4d8502Sjsg DECLARE_HASHTABLE(fences, 4); 47fb4d8502Sjsg }; 48fb4d8502Sjsg 49fb4d8502Sjsg void amdgpu_sync_create(struct amdgpu_sync *sync); 50ad8b1aafSjsg int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f); 51c349dbc7Sjsg int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, 52c349dbc7Sjsg struct dma_resv *resv, enum amdgpu_sync_mode mode, 53c349dbc7Sjsg void *owner); 54fb4d8502Sjsg struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, 55fb4d8502Sjsg struct amdgpu_ring *ring); 56ad8b1aafSjsg struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 57fb4d8502Sjsg int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone); 58*f005ef32Sjsg int amdgpu_sync_push_to_job(struct amdgpu_sync *sync, struct amdgpu_job *job); 59fb4d8502Sjsg int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr); 60fb4d8502Sjsg void amdgpu_sync_free(struct amdgpu_sync *sync); 61fb4d8502Sjsg int amdgpu_sync_init(void); 62fb4d8502Sjsg void amdgpu_sync_fini(void); 63fb4d8502Sjsg 64fb4d8502Sjsg #endif 65