xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1c349dbc7Sjsg /*
2c349dbc7Sjsg  * Copyright 2018 Advanced Micro Devices, Inc.
3c349dbc7Sjsg  *
4c349dbc7Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5c349dbc7Sjsg  * copy of this software and associated documentation files (the "Software"),
6c349dbc7Sjsg  * to deal in the Software without restriction, including without limitation
7c349dbc7Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c349dbc7Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9c349dbc7Sjsg  * Software is furnished to do so, subject to the following conditions:
10c349dbc7Sjsg  *
11c349dbc7Sjsg  * The above copyright notice and this permission notice shall be included in
12c349dbc7Sjsg  * all copies or substantial portions of the Software.
13c349dbc7Sjsg  *
14c349dbc7Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15c349dbc7Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16c349dbc7Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17c349dbc7Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18c349dbc7Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19c349dbc7Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20c349dbc7Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21c349dbc7Sjsg  *
22c349dbc7Sjsg  */
23c349dbc7Sjsg 
24c349dbc7Sjsg #ifndef __AMDGPU_SDMA_H__
25c349dbc7Sjsg #define __AMDGPU_SDMA_H__
261bb76ff1Sjsg #include "amdgpu_ras.h"
27c349dbc7Sjsg 
28c349dbc7Sjsg /* max number of IP instances */
29*f005ef32Sjsg #define AMDGPU_MAX_SDMA_INSTANCES		16
30c349dbc7Sjsg 
31c349dbc7Sjsg enum amdgpu_sdma_irq {
32c349dbc7Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE0  = 0,
33c349dbc7Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE1,
34c349dbc7Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE2,
35c349dbc7Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE3,
36c349dbc7Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE4,
37c349dbc7Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE5,
38c349dbc7Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE6,
39c349dbc7Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE7,
40*f005ef32Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE8,
41*f005ef32Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE9,
42*f005ef32Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE10,
43*f005ef32Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE11,
44*f005ef32Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE12,
45*f005ef32Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE13,
46*f005ef32Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE14,
47*f005ef32Sjsg 	AMDGPU_SDMA_IRQ_INSTANCE15,
48c349dbc7Sjsg 	AMDGPU_SDMA_IRQ_LAST
49c349dbc7Sjsg };
50c349dbc7Sjsg 
51*f005ef32Sjsg #define NUM_SDMA(x) hweight32(x)
52*f005ef32Sjsg 
53c349dbc7Sjsg struct amdgpu_sdma_instance {
54c349dbc7Sjsg 	/* SDMA firmware */
55c349dbc7Sjsg 	const struct firmware	*fw;
56c349dbc7Sjsg 	uint32_t		fw_version;
57c349dbc7Sjsg 	uint32_t		feature_version;
58c349dbc7Sjsg 
59c349dbc7Sjsg 	struct amdgpu_ring	ring;
60c349dbc7Sjsg 	struct amdgpu_ring	page;
61c349dbc7Sjsg 	bool			burst_nop;
62*f005ef32Sjsg 	uint32_t		aid_id;
63*f005ef32Sjsg };
64*f005ef32Sjsg 
65*f005ef32Sjsg enum amdgpu_sdma_ras_memory_id {
66*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF0 = 1,
67*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF1 = 2,
68*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF2 = 3,
69*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF3 = 4,
70*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF4 = 5,
71*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF5 = 6,
72*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF6 = 7,
73*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF7 = 8,
74*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF8 = 9,
75*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF9 = 10,
76*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF10 = 11,
77*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF11 = 12,
78*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF12 = 13,
79*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF13 = 14,
80*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF14 = 15,
81*f005ef32Sjsg 	AMDGPU_SDMA_MBANK_DATA_BUF15 = 16,
82*f005ef32Sjsg 	AMDGPU_SDMA_UCODE_BUF = 17,
83*f005ef32Sjsg 	AMDGPU_SDMA_RB_CMD_BUF = 18,
84*f005ef32Sjsg 	AMDGPU_SDMA_IB_CMD_BUF = 19,
85*f005ef32Sjsg 	AMDGPU_SDMA_UTCL1_RD_FIFO = 20,
86*f005ef32Sjsg 	AMDGPU_SDMA_UTCL1_RDBST_FIFO = 21,
87*f005ef32Sjsg 	AMDGPU_SDMA_UTCL1_WR_FIFO = 22,
88*f005ef32Sjsg 	AMDGPU_SDMA_DATA_LUT_FIFO = 23,
89*f005ef32Sjsg 	AMDGPU_SDMA_SPLIT_DAT_BUF = 24,
90*f005ef32Sjsg 	AMDGPU_SDMA_MEMORY_BLOCK_LAST,
91c349dbc7Sjsg };
92c349dbc7Sjsg 
931bb76ff1Sjsg struct amdgpu_sdma_ras {
941bb76ff1Sjsg 	struct amdgpu_ras_block_object ras_block;
95c349dbc7Sjsg };
96c349dbc7Sjsg 
97c349dbc7Sjsg struct amdgpu_sdma {
98c349dbc7Sjsg 	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
99c349dbc7Sjsg 	struct amdgpu_irq_src	trap_irq;
100c349dbc7Sjsg 	struct amdgpu_irq_src	illegal_inst_irq;
101c349dbc7Sjsg 	struct amdgpu_irq_src	ecc_irq;
1025ca02815Sjsg 	struct amdgpu_irq_src	vm_hole_irq;
1035ca02815Sjsg 	struct amdgpu_irq_src	doorbell_invalid_irq;
1045ca02815Sjsg 	struct amdgpu_irq_src	pool_timeout_irq;
1055ca02815Sjsg 	struct amdgpu_irq_src	srbm_write_irq;
1065ca02815Sjsg 
107c349dbc7Sjsg 	int			num_instances;
108*f005ef32Sjsg 	uint32_t 		sdma_mask;
109*f005ef32Sjsg 	int			num_inst_per_aid;
110c349dbc7Sjsg 	uint32_t                    srbm_soft_reset;
111c349dbc7Sjsg 	bool			has_page_queue;
112c349dbc7Sjsg 	struct ras_common_if	*ras_if;
1131bb76ff1Sjsg 	struct amdgpu_sdma_ras	*ras;
114c349dbc7Sjsg };
115c349dbc7Sjsg 
116c349dbc7Sjsg /*
117c349dbc7Sjsg  * Provided by hw blocks that can move/clear data.  e.g., gfx or sdma
118c349dbc7Sjsg  * But currently, we use sdma to move data.
119c349dbc7Sjsg  */
120c349dbc7Sjsg struct amdgpu_buffer_funcs {
121c349dbc7Sjsg 	/* maximum bytes in a single operation */
122c349dbc7Sjsg 	uint32_t	copy_max_bytes;
123c349dbc7Sjsg 
124c349dbc7Sjsg 	/* number of dw to reserve per operation */
125c349dbc7Sjsg 	unsigned	copy_num_dw;
126c349dbc7Sjsg 
127c349dbc7Sjsg 	/* used for buffer migration */
128c349dbc7Sjsg 	void (*emit_copy_buffer)(struct amdgpu_ib *ib,
129c349dbc7Sjsg 				 /* src addr in bytes */
130c349dbc7Sjsg 				 uint64_t src_offset,
131c349dbc7Sjsg 				 /* dst addr in bytes */
132c349dbc7Sjsg 				 uint64_t dst_offset,
133c349dbc7Sjsg 				 /* number of byte to transfer */
134ad8b1aafSjsg 				 uint32_t byte_count,
135ad8b1aafSjsg 				 bool tmz);
136c349dbc7Sjsg 
137c349dbc7Sjsg 	/* maximum bytes in a single operation */
138c349dbc7Sjsg 	uint32_t	fill_max_bytes;
139c349dbc7Sjsg 
140c349dbc7Sjsg 	/* number of dw to reserve per operation */
141c349dbc7Sjsg 	unsigned	fill_num_dw;
142c349dbc7Sjsg 
143c349dbc7Sjsg 	/* used for buffer clearing */
144c349dbc7Sjsg 	void (*emit_fill_buffer)(struct amdgpu_ib *ib,
145c349dbc7Sjsg 				 /* value to write to memory */
146c349dbc7Sjsg 				 uint32_t src_data,
147c349dbc7Sjsg 				 /* dst addr in bytes */
148c349dbc7Sjsg 				 uint64_t dst_offset,
149c349dbc7Sjsg 				 /* number of byte to fill */
150c349dbc7Sjsg 				 uint32_t byte_count);
151c349dbc7Sjsg };
152c349dbc7Sjsg 
153ad8b1aafSjsg #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b), (t))
154c349dbc7Sjsg #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
155c349dbc7Sjsg 
156c349dbc7Sjsg struct amdgpu_sdma_instance *
157c349dbc7Sjsg amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
158c349dbc7Sjsg int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
159c349dbc7Sjsg uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
160c349dbc7Sjsg int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
1611bb76ff1Sjsg 			      struct ras_common_if *ras_block);
162c349dbc7Sjsg int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
163c349dbc7Sjsg 		void *err_data,
164c349dbc7Sjsg 		struct amdgpu_iv_entry *entry);
165c349dbc7Sjsg int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
166c349dbc7Sjsg 				      struct amdgpu_irq_src *source,
167c349dbc7Sjsg 				      struct amdgpu_iv_entry *entry);
168*f005ef32Sjsg int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance,
169*f005ef32Sjsg 			       bool duplicate);
1701bb76ff1Sjsg void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev,
1711bb76ff1Sjsg         bool duplicate);
1721bb76ff1Sjsg void amdgpu_sdma_unset_buffer_funcs_helper(struct amdgpu_device *adev);
173*f005ef32Sjsg int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev);
1741bb76ff1Sjsg 
175c349dbc7Sjsg #endif
176