xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/amdgpu_sa.c (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1fb4d8502Sjsg /*
2fb4d8502Sjsg  * Copyright 2011 Red Hat Inc.
3fb4d8502Sjsg  * All Rights Reserved.
4fb4d8502Sjsg  *
5fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
6fb4d8502Sjsg  * copy of this software and associated documentation files (the
7fb4d8502Sjsg  * "Software"), to deal in the Software without restriction, including
8fb4d8502Sjsg  * without limitation the rights to use, copy, modify, merge, publish,
9fb4d8502Sjsg  * distribute, sub license, and/or sell copies of the Software, and to
10fb4d8502Sjsg  * permit persons to whom the Software is furnished to do so, subject to
11fb4d8502Sjsg  * the following conditions:
12fb4d8502Sjsg  *
13fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16fb4d8502Sjsg  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17fb4d8502Sjsg  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18fb4d8502Sjsg  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19fb4d8502Sjsg  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20fb4d8502Sjsg  *
21fb4d8502Sjsg  * The above copyright notice and this permission notice (including the
22fb4d8502Sjsg  * next paragraph) shall be included in all copies or substantial portions
23fb4d8502Sjsg  * of the Software.
24fb4d8502Sjsg  *
25fb4d8502Sjsg  */
26fb4d8502Sjsg /*
27fb4d8502Sjsg  * Authors:
28fb4d8502Sjsg  *    Jerome Glisse <glisse@freedesktop.org>
29fb4d8502Sjsg  */
30fb4d8502Sjsg /* Algorithm:
31fb4d8502Sjsg  *
32fb4d8502Sjsg  * We store the last allocated bo in "hole", we always try to allocate
33fb4d8502Sjsg  * after the last allocated bo. Principle is that in a linear GPU ring
34fb4d8502Sjsg  * progression was is after last is the oldest bo we allocated and thus
35fb4d8502Sjsg  * the first one that should no longer be in use by the GPU.
36fb4d8502Sjsg  *
37fb4d8502Sjsg  * If it's not the case we skip over the bo after last to the closest
38fb4d8502Sjsg  * done bo if such one exist. If none exist and we are not asked to
39fb4d8502Sjsg  * block we report failure to allocate.
40fb4d8502Sjsg  *
41fb4d8502Sjsg  * If we are asked to block we wait on all the oldest fence of all
42fb4d8502Sjsg  * rings. We just wait for any of those fence to complete.
43fb4d8502Sjsg  */
44c349dbc7Sjsg 
45fb4d8502Sjsg #include "amdgpu.h"
46fb4d8502Sjsg 
amdgpu_sa_bo_manager_init(struct amdgpu_device * adev,struct amdgpu_sa_manager * sa_manager,unsigned int size,u32 suballoc_align,u32 domain)47fb4d8502Sjsg int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
48fb4d8502Sjsg 			      struct amdgpu_sa_manager *sa_manager,
49*f005ef32Sjsg 			      unsigned int size, u32 suballoc_align, u32 domain)
50fb4d8502Sjsg {
51*f005ef32Sjsg 	int r;
52fb4d8502Sjsg 
53*f005ef32Sjsg 	r = amdgpu_bo_create_kernel(adev, size, AMDGPU_GPU_PAGE_SIZE, domain,
54*f005ef32Sjsg 				    &sa_manager->bo, &sa_manager->gpu_addr,
55*f005ef32Sjsg 				    &sa_manager->cpu_ptr);
56fb4d8502Sjsg 	if (r) {
57fb4d8502Sjsg 		dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
58fb4d8502Sjsg 		return r;
59fb4d8502Sjsg 	}
60fb4d8502Sjsg 
61*f005ef32Sjsg 	memset(sa_manager->cpu_ptr, 0, size);
62*f005ef32Sjsg 	drm_suballoc_manager_init(&sa_manager->base, size, suballoc_align);
63fb4d8502Sjsg 	return r;
64fb4d8502Sjsg }
65fb4d8502Sjsg 
amdgpu_sa_bo_manager_fini(struct amdgpu_device * adev,struct amdgpu_sa_manager * sa_manager)66fb4d8502Sjsg void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
67fb4d8502Sjsg 			       struct amdgpu_sa_manager *sa_manager)
68fb4d8502Sjsg {
69fb4d8502Sjsg 	if (sa_manager->bo == NULL) {
70fb4d8502Sjsg 		dev_err(adev->dev, "no bo for sa manager\n");
71fb4d8502Sjsg 		return;
72fb4d8502Sjsg 	}
73fb4d8502Sjsg 
74*f005ef32Sjsg 	drm_suballoc_manager_fini(&sa_manager->base);
75fb4d8502Sjsg 
76fb4d8502Sjsg 	amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr);
77fb4d8502Sjsg }
78fb4d8502Sjsg 
amdgpu_sa_bo_new(struct amdgpu_sa_manager * sa_manager,struct drm_suballoc ** sa_bo,unsigned int size)79fb4d8502Sjsg int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
80*f005ef32Sjsg 		     struct drm_suballoc **sa_bo,
81*f005ef32Sjsg 		     unsigned int size)
82fb4d8502Sjsg {
83*f005ef32Sjsg 	struct drm_suballoc *sa = drm_suballoc_new(&sa_manager->base, size,
84*f005ef32Sjsg 						   GFP_KERNEL, false, 0);
85fb4d8502Sjsg 
86*f005ef32Sjsg 	if (IS_ERR(sa)) {
87*f005ef32Sjsg 		*sa_bo = NULL;
88fb4d8502Sjsg 
89*f005ef32Sjsg 		return PTR_ERR(sa);
90*f005ef32Sjsg 	}
91fb4d8502Sjsg 
92*f005ef32Sjsg 	*sa_bo = sa;
93fb4d8502Sjsg 	return 0;
94fb4d8502Sjsg }
95fb4d8502Sjsg 
amdgpu_sa_bo_free(struct amdgpu_device * adev,struct drm_suballoc ** sa_bo,struct dma_fence * fence)96*f005ef32Sjsg void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct drm_suballoc **sa_bo,
97fb4d8502Sjsg 		       struct dma_fence *fence)
98fb4d8502Sjsg {
99fb4d8502Sjsg 	if (sa_bo == NULL || *sa_bo == NULL) {
100fb4d8502Sjsg 		return;
101fb4d8502Sjsg 	}
102fb4d8502Sjsg 
103*f005ef32Sjsg 	drm_suballoc_free(*sa_bo, fence);
104fb4d8502Sjsg 	*sa_bo = NULL;
105fb4d8502Sjsg }
106fb4d8502Sjsg 
107fb4d8502Sjsg #if defined(CONFIG_DEBUG_FS)
108fb4d8502Sjsg 
amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager * sa_manager,struct seq_file * m)109fb4d8502Sjsg void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
110fb4d8502Sjsg 				  struct seq_file *m)
111fb4d8502Sjsg {
112*f005ef32Sjsg 	struct drm_printer p = drm_seq_file_printer(m);
113fb4d8502Sjsg 
114*f005ef32Sjsg 	drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr);
115fb4d8502Sjsg }
116fb4d8502Sjsg #endif
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