1ad8b1aafSjsg /*
2ad8b1aafSjsg * Copyright 2020 Advanced Micro Devices, Inc.
3ad8b1aafSjsg *
4ad8b1aafSjsg * Permission is hereby granted, free of charge, to any person obtaining a
5ad8b1aafSjsg * copy of this software and associated documentation files (the "Software"),
6ad8b1aafSjsg * to deal in the Software without restriction, including without limitation
7ad8b1aafSjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8ad8b1aafSjsg * and/or sell copies of the Software, and to permit persons to whom the
9ad8b1aafSjsg * Software is furnished to do so, subject to the following conditions:
10ad8b1aafSjsg *
11ad8b1aafSjsg * The above copyright notice and this permission notice shall be included in
12ad8b1aafSjsg * all copies or substantial portions of the Software.
13ad8b1aafSjsg *
14ad8b1aafSjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15ad8b1aafSjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16ad8b1aafSjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17ad8b1aafSjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18ad8b1aafSjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19ad8b1aafSjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20ad8b1aafSjsg * OTHER DEALINGS IN THE SOFTWARE.
21ad8b1aafSjsg *
22ad8b1aafSjsg *
23ad8b1aafSjsg */
24ad8b1aafSjsg #include <linux/debugfs.h>
25ad8b1aafSjsg #include <linux/pm_runtime.h>
26ad8b1aafSjsg
27ad8b1aafSjsg #include "amdgpu.h"
28ad8b1aafSjsg #include "amdgpu_rap.h"
29ad8b1aafSjsg
30ad8b1aafSjsg #ifdef __linux__
31ad8b1aafSjsg
32ad8b1aafSjsg /**
33ad8b1aafSjsg * DOC: AMDGPU RAP debugfs test interface
34ad8b1aafSjsg *
35ad8b1aafSjsg * how to use?
36ad8b1aafSjsg * echo opcode > <debugfs_dir>/dri/xxx/rap_test
37ad8b1aafSjsg *
38ad8b1aafSjsg * opcode:
39ad8b1aafSjsg * currently, only 2 is supported by Linux host driver,
40ad8b1aafSjsg * opcode 2 stands for TA_CMD_RAP__VALIDATE_L0, used to
41ad8b1aafSjsg * trigger L0 policy validation, you can refer more detail
42ad8b1aafSjsg * from header file ta_rap_if.h
43ad8b1aafSjsg *
44ad8b1aafSjsg */
amdgpu_rap_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)45ad8b1aafSjsg static ssize_t amdgpu_rap_debugfs_write(struct file *f, const char __user *buf,
46ad8b1aafSjsg size_t size, loff_t *pos)
47ad8b1aafSjsg {
48ad8b1aafSjsg struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
49ad8b1aafSjsg struct ta_rap_shared_memory *rap_shared_mem;
50ad8b1aafSjsg struct ta_rap_cmd_output_data *rap_cmd_output;
51ad8b1aafSjsg struct drm_device *dev = adev_to_drm(adev);
52ad8b1aafSjsg uint32_t op;
53*5ca02815Sjsg enum ta_rap_status status;
54ad8b1aafSjsg int ret;
55ad8b1aafSjsg
56ad8b1aafSjsg if (*pos || size != 2)
57ad8b1aafSjsg return -EINVAL;
58ad8b1aafSjsg
59ad8b1aafSjsg ret = kstrtouint_from_user(buf, size, *pos, &op);
60ad8b1aafSjsg if (ret)
61ad8b1aafSjsg return ret;
62ad8b1aafSjsg
63ad8b1aafSjsg ret = pm_runtime_get_sync(dev->dev);
64ad8b1aafSjsg if (ret < 0) {
65ad8b1aafSjsg pm_runtime_put_autosuspend(dev->dev);
66ad8b1aafSjsg return ret;
67ad8b1aafSjsg }
68ad8b1aafSjsg
69ad8b1aafSjsg /* make sure gfx core is on, RAP TA cann't handle
70ad8b1aafSjsg * GFX OFF case currently.
71ad8b1aafSjsg */
72ad8b1aafSjsg amdgpu_gfx_off_ctrl(adev, false);
73ad8b1aafSjsg
74ad8b1aafSjsg switch (op) {
75ad8b1aafSjsg case 2:
76*5ca02815Sjsg ret = psp_rap_invoke(&adev->psp, op, &status);
77*5ca02815Sjsg if (!ret && status == TA_RAP_STATUS__SUCCESS) {
78ad8b1aafSjsg dev_info(adev->dev, "RAP L0 validate test success.\n");
79ad8b1aafSjsg } else {
80ad8b1aafSjsg rap_shared_mem = (struct ta_rap_shared_memory *)
81*5ca02815Sjsg adev->psp.rap_context.context.mem_context.shared_buf;
82ad8b1aafSjsg rap_cmd_output = &(rap_shared_mem->rap_out_message.output);
83ad8b1aafSjsg
84ad8b1aafSjsg dev_info(adev->dev, "RAP test failed, the output is:\n");
85ad8b1aafSjsg dev_info(adev->dev, "\tlast_subsection: 0x%08x.\n",
86ad8b1aafSjsg rap_cmd_output->last_subsection);
87ad8b1aafSjsg dev_info(adev->dev, "\tnum_total_validate: 0x%08x.\n",
88ad8b1aafSjsg rap_cmd_output->num_total_validate);
89ad8b1aafSjsg dev_info(adev->dev, "\tnum_valid: 0x%08x.\n",
90ad8b1aafSjsg rap_cmd_output->num_valid);
91ad8b1aafSjsg dev_info(adev->dev, "\tlast_validate_addr: 0x%08x.\n",
92ad8b1aafSjsg rap_cmd_output->last_validate_addr);
93ad8b1aafSjsg dev_info(adev->dev, "\tlast_validate_val: 0x%08x.\n",
94ad8b1aafSjsg rap_cmd_output->last_validate_val);
95ad8b1aafSjsg dev_info(adev->dev, "\tlast_validate_val_exptd: 0x%08x.\n",
96ad8b1aafSjsg rap_cmd_output->last_validate_val_exptd);
97ad8b1aafSjsg }
98ad8b1aafSjsg break;
99ad8b1aafSjsg default:
100ad8b1aafSjsg dev_info(adev->dev, "Unsupported op id: %d, ", op);
101ad8b1aafSjsg dev_info(adev->dev, "Only support op 2(L0 validate test).\n");
102*5ca02815Sjsg break;
103ad8b1aafSjsg }
104ad8b1aafSjsg
105ad8b1aafSjsg amdgpu_gfx_off_ctrl(adev, true);
106ad8b1aafSjsg pm_runtime_mark_last_busy(dev->dev);
107ad8b1aafSjsg pm_runtime_put_autosuspend(dev->dev);
108ad8b1aafSjsg
109ad8b1aafSjsg return size;
110ad8b1aafSjsg }
111ad8b1aafSjsg
112ad8b1aafSjsg static const struct file_operations amdgpu_rap_debugfs_ops = {
113ad8b1aafSjsg .owner = THIS_MODULE,
114ad8b1aafSjsg .read = NULL,
115ad8b1aafSjsg .write = amdgpu_rap_debugfs_write,
116ad8b1aafSjsg .llseek = default_llseek
117ad8b1aafSjsg };
118ad8b1aafSjsg
119ad8b1aafSjsg #endif /* __linux__ */
120ad8b1aafSjsg
amdgpu_rap_debugfs_init(struct amdgpu_device * adev)121ad8b1aafSjsg void amdgpu_rap_debugfs_init(struct amdgpu_device *adev)
122ad8b1aafSjsg {
123ad8b1aafSjsg struct drm_minor *minor = adev_to_drm(adev)->primary;
124ad8b1aafSjsg
125*5ca02815Sjsg if (!adev->psp.rap_context.context.initialized)
126ad8b1aafSjsg return;
127ad8b1aafSjsg
128ad8b1aafSjsg debugfs_create_file("rap_test", S_IWUSR, minor->debugfs_root,
129ad8b1aafSjsg adev, &amdgpu_rap_debugfs_ops);
130ad8b1aafSjsg }
131