1c349dbc7Sjsg /* 2c349dbc7Sjsg * Copyright 2019 Advanced Micro Devices, Inc. 3c349dbc7Sjsg * 4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"), 6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation 7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions: 10c349dbc7Sjsg * 11c349dbc7Sjsg * The above copyright notice and this permission notice shall be included in 12c349dbc7Sjsg * all copies or substantial portions of the Software. 13c349dbc7Sjsg * 14c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c349dbc7Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c349dbc7Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c349dbc7Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21c349dbc7Sjsg * 22c349dbc7Sjsg */ 23c349dbc7Sjsg 24c349dbc7Sjsg #ifndef _AMDGPU_PMU_H_ 25c349dbc7Sjsg #define _AMDGPU_PMU_H_ 26c349dbc7Sjsg 27*5ca02815Sjsg /* PMU types. */ 28c349dbc7Sjsg enum amdgpu_pmu_perf_type { 29*5ca02815Sjsg AMDGPU_PMU_PERF_TYPE_NONE = 0, 30*5ca02815Sjsg AMDGPU_PMU_PERF_TYPE_DF, 31*5ca02815Sjsg AMDGPU_PMU_PERF_TYPE_ALL 32c349dbc7Sjsg }; 33c349dbc7Sjsg 34*5ca02815Sjsg /* 35*5ca02815Sjsg * PMU type AMDGPU_PMU_PERF_TYPE_ALL can hold events of different "type" 36*5ca02815Sjsg * configurations. Event config types are parsed from the 64-bit raw 37*5ca02815Sjsg * config (See EVENT_CONFIG_TYPE_SHIFT and EVENT_CONFIG_TYPE_MASK) and 38*5ca02815Sjsg * are registered into the HW perf events config_base. 39*5ca02815Sjsg * 40*5ca02815Sjsg * PMU types with only a single event configuration type 41*5ca02815Sjsg * (non-AMDGPU_PMU_PERF_TYPE_ALL) have their event config type auto generated 42*5ca02815Sjsg * when the performance counter is added. 43*5ca02815Sjsg */ 44*5ca02815Sjsg enum amdgpu_pmu_event_config_type { 45*5ca02815Sjsg AMDGPU_PMU_EVENT_CONFIG_TYPE_NONE = 0, 46*5ca02815Sjsg AMDGPU_PMU_EVENT_CONFIG_TYPE_DF, 47*5ca02815Sjsg AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI, 48*5ca02815Sjsg AMDGPU_PMU_EVENT_CONFIG_TYPE_MAX 49*5ca02815Sjsg }; 50*5ca02815Sjsg 51*5ca02815Sjsg #define AMDGPU_PMU_EVENT_CONFIG_TYPE_SHIFT 56 52*5ca02815Sjsg #define AMDGPU_PMU_EVENT_CONFIG_TYPE_MASK 0xff 53*5ca02815Sjsg 54c349dbc7Sjsg int amdgpu_pmu_init(struct amdgpu_device *adev); 55c349dbc7Sjsg void amdgpu_pmu_fini(struct amdgpu_device *adev); 56c349dbc7Sjsg 57c349dbc7Sjsg #endif /* _AMDGPU_PMU_H_ */ 58