1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 #include "amdgpu_amdkfd.h" 40 41 /** 42 * DOC: amdgpu_object 43 * 44 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 45 * represents memory used by driver (VRAM, system memory, etc.). The driver 46 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 47 * to create/destroy/set buffer object which are then managed by the kernel TTM 48 * memory manager. 49 * The interfaces are also used internally by kernel clients, including gfx, 50 * uvd, etc. for kernel managed allocations used by the GPU. 51 * 52 */ 53 54 static bool amdgpu_bo_need_backup(struct amdgpu_device *adev) 55 { 56 if (adev->flags & AMD_IS_APU) 57 return false; 58 59 if (amdgpu_gpu_recovery == 0 || 60 (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev))) 61 return false; 62 63 return true; 64 } 65 66 /** 67 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 68 * 69 * @bo: &amdgpu_bo buffer object 70 * 71 * This function is called when a BO stops being pinned, and updates the 72 * &amdgpu_device pin_size values accordingly. 73 */ 74 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 75 { 76 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 77 78 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 79 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 80 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 81 &adev->visible_pin_size); 82 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 83 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 84 } 85 } 86 87 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 88 { 89 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 90 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 91 92 if (bo->pin_count > 0) 93 amdgpu_bo_subtract_pin_size(bo); 94 95 if (bo->kfd_bo) 96 amdgpu_amdkfd_unreserve_system_memory_limit(bo); 97 98 amdgpu_bo_kunmap(bo); 99 100 if (bo->gem_base.import_attach) 101 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg); 102 drm_gem_object_release(&bo->gem_base); 103 amdgpu_bo_unref(&bo->parent); 104 if (!list_empty(&bo->shadow_list)) { 105 mutex_lock(&adev->shadow_list_lock); 106 list_del_init(&bo->shadow_list); 107 mutex_unlock(&adev->shadow_list_lock); 108 } 109 kfree(bo->metadata); 110 pool_put(&bo->adev->ddev->objpl, bo); 111 } 112 113 /** 114 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 115 * @bo: buffer object to be checked 116 * 117 * Uses destroy function associated with the object to determine if this is 118 * an &amdgpu_bo. 119 * 120 * Returns: 121 * true if the object belongs to &amdgpu_bo, false if not. 122 */ 123 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 124 { 125 if (bo->destroy == &amdgpu_bo_destroy) 126 return true; 127 return false; 128 } 129 130 /** 131 * amdgpu_bo_placement_from_domain - set buffer's placement 132 * @abo: &amdgpu_bo buffer object whose placement is to be set 133 * @domain: requested domain 134 * 135 * Sets buffer's placement according to requested domain and the buffer's 136 * flags. 137 */ 138 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 139 { 140 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 141 struct ttm_placement *placement = &abo->placement; 142 struct ttm_place *places = abo->placements; 143 u64 flags = abo->flags; 144 u32 c = 0; 145 146 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 147 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 148 149 places[c].fpfn = 0; 150 places[c].lpfn = 0; 151 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 152 TTM_PL_FLAG_VRAM; 153 154 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 155 places[c].lpfn = visible_pfn; 156 else 157 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 158 159 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 160 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 161 c++; 162 } 163 164 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 165 places[c].fpfn = 0; 166 if (flags & AMDGPU_GEM_CREATE_SHADOW) 167 places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 168 else 169 places[c].lpfn = 0; 170 places[c].flags = TTM_PL_FLAG_TT; 171 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 172 places[c].flags |= TTM_PL_FLAG_WC | 173 TTM_PL_FLAG_UNCACHED; 174 else 175 places[c].flags |= TTM_PL_FLAG_CACHED; 176 c++; 177 } 178 179 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 180 places[c].fpfn = 0; 181 places[c].lpfn = 0; 182 places[c].flags = TTM_PL_FLAG_SYSTEM; 183 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 184 places[c].flags |= TTM_PL_FLAG_WC | 185 TTM_PL_FLAG_UNCACHED; 186 else 187 places[c].flags |= TTM_PL_FLAG_CACHED; 188 c++; 189 } 190 191 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 192 places[c].fpfn = 0; 193 places[c].lpfn = 0; 194 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 195 c++; 196 } 197 198 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 199 places[c].fpfn = 0; 200 places[c].lpfn = 0; 201 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 202 c++; 203 } 204 205 if (domain & AMDGPU_GEM_DOMAIN_OA) { 206 places[c].fpfn = 0; 207 places[c].lpfn = 0; 208 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 209 c++; 210 } 211 212 if (!c) { 213 places[c].fpfn = 0; 214 places[c].lpfn = 0; 215 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 216 c++; 217 } 218 219 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 220 221 placement->num_placement = c; 222 placement->placement = places; 223 224 placement->num_busy_placement = c; 225 placement->busy_placement = places; 226 } 227 228 /** 229 * amdgpu_bo_create_reserved - create reserved BO for kernel use 230 * 231 * @adev: amdgpu device object 232 * @size: size for the new BO 233 * @align: alignment for the new BO 234 * @domain: where to place it 235 * @bo_ptr: used to initialize BOs in structures 236 * @gpu_addr: GPU addr of the pinned BO 237 * @cpu_addr: optional CPU address mapping 238 * 239 * Allocates and pins a BO for kernel internal use, and returns it still 240 * reserved. 241 * 242 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 243 * 244 * Returns: 245 * 0 on success, negative error code otherwise. 246 */ 247 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 248 unsigned long size, int align, 249 u32 domain, struct amdgpu_bo **bo_ptr, 250 u64 *gpu_addr, void **cpu_addr) 251 { 252 struct amdgpu_bo_param bp; 253 bool free = false; 254 int r; 255 256 memset(&bp, 0, sizeof(bp)); 257 bp.size = size; 258 bp.byte_align = align; 259 bp.domain = domain; 260 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 261 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 262 bp.type = ttm_bo_type_kernel; 263 bp.resv = NULL; 264 265 if (!*bo_ptr) { 266 r = amdgpu_bo_create(adev, &bp, bo_ptr); 267 if (r) { 268 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 269 r); 270 return r; 271 } 272 free = true; 273 } 274 275 r = amdgpu_bo_reserve(*bo_ptr, false); 276 if (r) { 277 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 278 goto error_free; 279 } 280 281 r = amdgpu_bo_pin(*bo_ptr, domain); 282 if (r) { 283 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 284 goto error_unreserve; 285 } 286 287 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 288 if (r) { 289 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 290 goto error_unpin; 291 } 292 293 if (gpu_addr) 294 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 295 296 if (cpu_addr) { 297 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 298 if (r) { 299 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 300 goto error_unpin; 301 } 302 } 303 304 return 0; 305 306 error_unpin: 307 amdgpu_bo_unpin(*bo_ptr); 308 error_unreserve: 309 amdgpu_bo_unreserve(*bo_ptr); 310 311 error_free: 312 if (free) 313 amdgpu_bo_unref(bo_ptr); 314 315 return r; 316 } 317 318 /** 319 * amdgpu_bo_create_kernel - create BO for kernel use 320 * 321 * @adev: amdgpu device object 322 * @size: size for the new BO 323 * @align: alignment for the new BO 324 * @domain: where to place it 325 * @bo_ptr: used to initialize BOs in structures 326 * @gpu_addr: GPU addr of the pinned BO 327 * @cpu_addr: optional CPU address mapping 328 * 329 * Allocates and pins a BO for kernel internal use. 330 * 331 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 332 * 333 * Returns: 334 * 0 on success, negative error code otherwise. 335 */ 336 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 337 unsigned long size, int align, 338 u32 domain, struct amdgpu_bo **bo_ptr, 339 u64 *gpu_addr, void **cpu_addr) 340 { 341 int r; 342 343 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 344 gpu_addr, cpu_addr); 345 346 if (r) 347 return r; 348 349 amdgpu_bo_unreserve(*bo_ptr); 350 351 return 0; 352 } 353 354 /** 355 * amdgpu_bo_free_kernel - free BO for kernel use 356 * 357 * @bo: amdgpu BO to free 358 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 359 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 360 * 361 * unmaps and unpin a BO for kernel internal use. 362 */ 363 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 364 void **cpu_addr) 365 { 366 if (*bo == NULL) 367 return; 368 369 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 370 if (cpu_addr) 371 amdgpu_bo_kunmap(*bo); 372 373 amdgpu_bo_unpin(*bo); 374 amdgpu_bo_unreserve(*bo); 375 } 376 amdgpu_bo_unref(bo); 377 378 if (gpu_addr) 379 *gpu_addr = 0; 380 381 if (cpu_addr) 382 *cpu_addr = NULL; 383 } 384 385 /* Validate bo size is bit bigger then the request domain */ 386 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 387 unsigned long size, u32 domain) 388 { 389 struct ttm_mem_type_manager *man = NULL; 390 391 /* 392 * If GTT is part of requested domains the check must succeed to 393 * allow fall back to GTT 394 */ 395 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 396 man = &adev->mman.bdev.man[TTM_PL_TT]; 397 398 if (size < (man->size << PAGE_SHIFT)) 399 return true; 400 else 401 goto fail; 402 } 403 404 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 405 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 406 407 if (size < (man->size << PAGE_SHIFT)) 408 return true; 409 else 410 goto fail; 411 } 412 413 414 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 415 return true; 416 417 fail: 418 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 419 man->size << PAGE_SHIFT); 420 return false; 421 } 422 423 #ifdef __amd64__ 424 #define CONFIG_X86 1 425 #define CONFIG_X86_64 1 426 #define CONFIG_X86_PAT 1 427 #endif 428 429 #ifdef __i386__ 430 #define CONFIG_X86 1 431 #define CONFIG_X86_32 1 432 #define CONFIG_X86_PAT 1 433 #endif 434 435 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 436 struct amdgpu_bo_param *bp, 437 struct amdgpu_bo **bo_ptr) 438 { 439 struct ttm_operation_ctx ctx = { 440 .interruptible = (bp->type != ttm_bo_type_kernel), 441 .no_wait_gpu = false, 442 .resv = bp->resv, 443 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT 444 }; 445 struct amdgpu_bo *bo; 446 unsigned long page_align, size = bp->size; 447 size_t acc_size; 448 int r; 449 450 page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 451 size = roundup2(size, PAGE_SIZE); 452 453 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 454 return -ENOMEM; 455 456 *bo_ptr = NULL; 457 458 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 459 sizeof(struct amdgpu_bo)); 460 461 bo = pool_get(&adev->ddev->objpl, PR_WAITOK | PR_ZERO); 462 if (bo == NULL) 463 return -ENOMEM; 464 drm_gem_private_object_init(adev->ddev, &bo->gem_base, size); 465 bo->adev = adev; 466 INIT_LIST_HEAD(&bo->shadow_list); 467 INIT_LIST_HEAD(&bo->va); 468 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 469 bp->domain; 470 bo->allowed_domains = bo->preferred_domains; 471 if (bp->type != ttm_bo_type_kernel && 472 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 473 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 474 475 bo->flags = bp->flags; 476 477 #ifdef CONFIG_X86_32 478 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 479 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 480 */ 481 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 482 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 483 /* Don't try to enable write-combining when it can't work, or things 484 * may be slow 485 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 486 */ 487 488 #ifndef CONFIG_COMPILE_TEST 489 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 490 thanks to write-combining 491 #endif 492 493 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 494 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 495 "better performance thanks to write-combining\n"); 496 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 497 #else 498 /* For architectures that don't support WC memory, 499 * mask out the WC flag from the BO 500 */ 501 if (!drm_arch_can_wc_memory()) 502 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 503 #endif 504 505 bo->tbo.bdev = &adev->mman.bdev; 506 amdgpu_bo_placement_from_domain(bo, bp->domain); 507 if (bp->type == ttm_bo_type_kernel) 508 bo->tbo.priority = 1; 509 510 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 511 &bo->placement, page_align, &ctx, acc_size, 512 NULL, bp->resv, &amdgpu_bo_destroy); 513 if (unlikely(r != 0)) 514 return r; 515 516 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 517 bo->tbo.mem.mem_type == TTM_PL_VRAM && 518 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 519 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 520 ctx.bytes_moved); 521 else 522 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 523 524 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 525 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 526 struct dma_fence *fence; 527 528 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); 529 if (unlikely(r)) 530 goto fail_unreserve; 531 532 amdgpu_bo_fence(bo, fence, false); 533 dma_fence_put(bo->tbo.moving); 534 bo->tbo.moving = dma_fence_get(fence); 535 dma_fence_put(fence); 536 } 537 if (!bp->resv) 538 amdgpu_bo_unreserve(bo); 539 *bo_ptr = bo; 540 541 trace_amdgpu_bo_create(bo); 542 543 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 544 if (bp->type == ttm_bo_type_device) 545 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 546 547 return 0; 548 549 fail_unreserve: 550 if (!bp->resv) 551 ww_mutex_unlock(&bo->tbo.resv->lock); 552 amdgpu_bo_unref(&bo); 553 return r; 554 } 555 556 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 557 unsigned long size, int byte_align, 558 struct amdgpu_bo *bo) 559 { 560 struct amdgpu_bo_param bp; 561 int r; 562 563 if (bo->shadow) 564 return 0; 565 566 memset(&bp, 0, sizeof(bp)); 567 bp.size = size; 568 bp.byte_align = byte_align; 569 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 570 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 571 AMDGPU_GEM_CREATE_SHADOW; 572 bp.type = ttm_bo_type_kernel; 573 bp.resv = bo->tbo.resv; 574 575 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 576 if (!r) { 577 bo->shadow->parent = amdgpu_bo_ref(bo); 578 mutex_lock(&adev->shadow_list_lock); 579 list_add_tail(&bo->shadow_list, &adev->shadow_list); 580 mutex_unlock(&adev->shadow_list_lock); 581 } 582 583 return r; 584 } 585 586 /** 587 * amdgpu_bo_create - create an &amdgpu_bo buffer object 588 * @adev: amdgpu device object 589 * @bp: parameters to be used for the buffer object 590 * @bo_ptr: pointer to the buffer object pointer 591 * 592 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 593 * shadow object. 594 * Shadow object is used to backup the original buffer object, and is always 595 * in GTT. 596 * 597 * Returns: 598 * 0 for success or a negative error code on failure. 599 */ 600 int amdgpu_bo_create(struct amdgpu_device *adev, 601 struct amdgpu_bo_param *bp, 602 struct amdgpu_bo **bo_ptr) 603 { 604 u64 flags = bp->flags; 605 int r; 606 607 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 608 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 609 if (r) 610 return r; 611 612 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_bo_need_backup(adev)) { 613 if (!bp->resv) 614 WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv, 615 NULL)); 616 617 r = amdgpu_bo_create_shadow(adev, bp->size, bp->byte_align, (*bo_ptr)); 618 619 if (!bp->resv) 620 reservation_object_unlock((*bo_ptr)->tbo.resv); 621 622 if (r) 623 amdgpu_bo_unref(bo_ptr); 624 } 625 626 return r; 627 } 628 629 /** 630 * amdgpu_bo_backup_to_shadow - Backs up an &amdgpu_bo buffer object 631 * @adev: amdgpu device object 632 * @ring: amdgpu_ring for the engine handling the buffer operations 633 * @bo: &amdgpu_bo buffer to be backed up 634 * @resv: reservation object with embedded fence 635 * @fence: dma_fence associated with the operation 636 * @direct: whether to submit the job directly 637 * 638 * Copies an &amdgpu_bo buffer object to its shadow object. 639 * Not used for now. 640 * 641 * Returns: 642 * 0 for success or a negative error code on failure. 643 */ 644 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, 645 struct amdgpu_ring *ring, 646 struct amdgpu_bo *bo, 647 struct reservation_object *resv, 648 struct dma_fence **fence, 649 bool direct) 650 651 { 652 struct amdgpu_bo *shadow = bo->shadow; 653 uint64_t bo_addr, shadow_addr; 654 int r; 655 656 if (!shadow) 657 return -EINVAL; 658 659 bo_addr = amdgpu_bo_gpu_offset(bo); 660 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 661 662 r = reservation_object_reserve_shared(bo->tbo.resv); 663 if (r) 664 goto err; 665 666 r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr, 667 amdgpu_bo_size(bo), resv, fence, 668 direct, false); 669 if (!r) 670 amdgpu_bo_fence(bo, *fence, true); 671 672 err: 673 return r; 674 } 675 676 /** 677 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 678 * @bo: pointer to the buffer object 679 * 680 * Sets placement according to domain; and changes placement and caching 681 * policy of the buffer object according to the placement. 682 * This is used for validating shadow bos. It calls ttm_bo_validate() to 683 * make sure the buffer is resident where it needs to be. 684 * 685 * Returns: 686 * 0 for success or a negative error code on failure. 687 */ 688 int amdgpu_bo_validate(struct amdgpu_bo *bo) 689 { 690 struct ttm_operation_ctx ctx = { false, false }; 691 uint32_t domain; 692 int r; 693 694 if (bo->pin_count) 695 return 0; 696 697 domain = bo->preferred_domains; 698 699 retry: 700 amdgpu_bo_placement_from_domain(bo, domain); 701 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 702 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 703 domain = bo->allowed_domains; 704 goto retry; 705 } 706 707 return r; 708 } 709 710 /** 711 * amdgpu_bo_restore_from_shadow - restore an &amdgpu_bo buffer object 712 * @adev: amdgpu device object 713 * @ring: amdgpu_ring for the engine handling the buffer operations 714 * @bo: &amdgpu_bo buffer to be restored 715 * @resv: reservation object with embedded fence 716 * @fence: dma_fence associated with the operation 717 * @direct: whether to submit the job directly 718 * 719 * Copies a buffer object's shadow content back to the object. 720 * This is used for recovering a buffer from its shadow in case of a gpu 721 * reset where vram context may be lost. 722 * 723 * Returns: 724 * 0 for success or a negative error code on failure. 725 */ 726 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, 727 struct amdgpu_ring *ring, 728 struct amdgpu_bo *bo, 729 struct reservation_object *resv, 730 struct dma_fence **fence, 731 bool direct) 732 733 { 734 struct amdgpu_bo *shadow = bo->shadow; 735 uint64_t bo_addr, shadow_addr; 736 int r; 737 738 if (!shadow) 739 return -EINVAL; 740 741 bo_addr = amdgpu_bo_gpu_offset(bo); 742 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 743 744 r = reservation_object_reserve_shared(bo->tbo.resv); 745 if (r) 746 goto err; 747 748 r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr, 749 amdgpu_bo_size(bo), resv, fence, 750 direct, false); 751 if (!r) 752 amdgpu_bo_fence(bo, *fence, true); 753 754 err: 755 return r; 756 } 757 758 /** 759 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 760 * @bo: &amdgpu_bo buffer object to be mapped 761 * @ptr: kernel virtual address to be returned 762 * 763 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 764 * amdgpu_bo_kptr() to get the kernel virtual address. 765 * 766 * Returns: 767 * 0 for success or a negative error code on failure. 768 */ 769 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 770 { 771 void *kptr; 772 long r; 773 774 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 775 return -EPERM; 776 777 kptr = amdgpu_bo_kptr(bo); 778 if (kptr) { 779 if (ptr) 780 *ptr = kptr; 781 return 0; 782 } 783 784 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false, 785 MAX_SCHEDULE_TIMEOUT); 786 if (r < 0) 787 return r; 788 789 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 790 if (r) 791 return r; 792 793 if (ptr) 794 *ptr = amdgpu_bo_kptr(bo); 795 796 return 0; 797 } 798 799 /** 800 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 801 * @bo: &amdgpu_bo buffer object 802 * 803 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 804 * 805 * Returns: 806 * the virtual address of a buffer object area. 807 */ 808 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 809 { 810 bool is_iomem; 811 812 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 813 } 814 815 /** 816 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 817 * @bo: &amdgpu_bo buffer object to be unmapped 818 * 819 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 820 */ 821 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 822 { 823 if (bo->kmap.bo) 824 ttm_bo_kunmap(&bo->kmap); 825 } 826 827 /** 828 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 829 * @bo: &amdgpu_bo buffer object 830 * 831 * References the contained &ttm_buffer_object. 832 * 833 * Returns: 834 * a refcounted pointer to the &amdgpu_bo buffer object. 835 */ 836 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 837 { 838 if (bo == NULL) 839 return NULL; 840 841 ttm_bo_get(&bo->tbo); 842 return bo; 843 } 844 845 /** 846 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 847 * @bo: &amdgpu_bo buffer object 848 * 849 * Unreferences the contained &ttm_buffer_object and clear the pointer 850 */ 851 void amdgpu_bo_unref(struct amdgpu_bo **bo) 852 { 853 struct ttm_buffer_object *tbo; 854 855 if ((*bo) == NULL) 856 return; 857 858 tbo = &((*bo)->tbo); 859 ttm_bo_put(tbo); 860 *bo = NULL; 861 } 862 863 /** 864 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 865 * @bo: &amdgpu_bo buffer object to be pinned 866 * @domain: domain to be pinned to 867 * @min_offset: the start of requested address range 868 * @max_offset: the end of requested address range 869 * 870 * Pins the buffer object according to requested domain and address range. If 871 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 872 * pin_count and pin_size accordingly. 873 * 874 * Pinning means to lock pages in memory along with keeping them at a fixed 875 * offset. It is required when a buffer can not be moved, for example, when 876 * a display buffer is being scanned out. 877 * 878 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 879 * where to pin a buffer if there are specific restrictions on where a buffer 880 * must be located. 881 * 882 * Returns: 883 * 0 for success or a negative error code on failure. 884 */ 885 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 886 u64 min_offset, u64 max_offset) 887 { 888 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 889 struct ttm_operation_ctx ctx = { false, false }; 890 int r, i; 891 892 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 893 return -EPERM; 894 895 if (WARN_ON_ONCE(min_offset > max_offset)) 896 return -EINVAL; 897 898 /* A shared bo cannot be migrated to VRAM */ 899 if (bo->prime_shared_count) { 900 if (domain & AMDGPU_GEM_DOMAIN_GTT) 901 domain = AMDGPU_GEM_DOMAIN_GTT; 902 else 903 return -EINVAL; 904 } 905 906 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 907 * See function amdgpu_display_supported_domains() 908 */ 909 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 910 911 if (bo->pin_count) { 912 uint32_t mem_type = bo->tbo.mem.mem_type; 913 914 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 915 return -EINVAL; 916 917 bo->pin_count++; 918 919 if (max_offset != 0) { 920 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 921 WARN_ON_ONCE(max_offset < 922 (amdgpu_bo_gpu_offset(bo) - domain_start)); 923 } 924 925 return 0; 926 } 927 928 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 929 /* force to pin into visible video ram */ 930 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 931 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 932 amdgpu_bo_placement_from_domain(bo, domain); 933 for (i = 0; i < bo->placement.num_placement; i++) { 934 unsigned fpfn, lpfn; 935 936 fpfn = min_offset >> PAGE_SHIFT; 937 lpfn = max_offset >> PAGE_SHIFT; 938 939 if (fpfn > bo->placements[i].fpfn) 940 bo->placements[i].fpfn = fpfn; 941 if (!bo->placements[i].lpfn || 942 (lpfn && lpfn < bo->placements[i].lpfn)) 943 bo->placements[i].lpfn = lpfn; 944 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 945 } 946 947 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 948 if (unlikely(r)) { 949 dev_err(adev->dev, "%p pin failed\n", bo); 950 goto error; 951 } 952 953 bo->pin_count = 1; 954 955 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 956 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 957 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 958 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 959 &adev->visible_pin_size); 960 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 961 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 962 } 963 964 error: 965 return r; 966 } 967 968 /** 969 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 970 * @bo: &amdgpu_bo buffer object to be pinned 971 * @domain: domain to be pinned to 972 * 973 * A simple wrapper to amdgpu_bo_pin_restricted(). 974 * Provides a simpler API for buffers that do not have any strict restrictions 975 * on where a buffer must be located. 976 * 977 * Returns: 978 * 0 for success or a negative error code on failure. 979 */ 980 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 981 { 982 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 983 } 984 985 /** 986 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 987 * @bo: &amdgpu_bo buffer object to be unpinned 988 * 989 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 990 * Changes placement and pin size accordingly. 991 * 992 * Returns: 993 * 0 for success or a negative error code on failure. 994 */ 995 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 996 { 997 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 998 struct ttm_operation_ctx ctx = { false, false }; 999 int r, i; 1000 1001 if (!bo->pin_count) { 1002 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 1003 return 0; 1004 } 1005 bo->pin_count--; 1006 if (bo->pin_count) 1007 return 0; 1008 1009 amdgpu_bo_subtract_pin_size(bo); 1010 1011 for (i = 0; i < bo->placement.num_placement; i++) { 1012 bo->placements[i].lpfn = 0; 1013 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 1014 } 1015 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1016 if (unlikely(r)) 1017 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 1018 1019 return r; 1020 } 1021 1022 /** 1023 * amdgpu_bo_evict_vram - evict VRAM buffers 1024 * @adev: amdgpu device object 1025 * 1026 * Evicts all VRAM buffers on the lru list of the memory type. 1027 * Mainly used for evicting vram at suspend time. 1028 * 1029 * Returns: 1030 * 0 for success or a negative error code on failure. 1031 */ 1032 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 1033 { 1034 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 1035 if (0 && (adev->flags & AMD_IS_APU)) { 1036 /* Useless to evict on IGP chips */ 1037 return 0; 1038 } 1039 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 1040 } 1041 1042 static const char *amdgpu_vram_names[] = { 1043 "UNKNOWN", 1044 "GDDR1", 1045 "DDR2", 1046 "GDDR3", 1047 "GDDR4", 1048 "GDDR5", 1049 "HBM", 1050 "DDR3", 1051 "DDR4", 1052 }; 1053 1054 /** 1055 * amdgpu_bo_init - initialize memory manager 1056 * @adev: amdgpu device object 1057 * 1058 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1059 * 1060 * Returns: 1061 * 0 for success or a negative error code on failure. 1062 */ 1063 int amdgpu_bo_init(struct amdgpu_device *adev) 1064 { 1065 paddr_t start, end; 1066 1067 #ifdef __linux__ 1068 /* reserve PAT memory space to WC for VRAM */ 1069 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1070 adev->gmc.aper_size); 1071 1072 /* Add an MTRR for the VRAM */ 1073 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1074 adev->gmc.aper_size); 1075 #else 1076 drm_mtrr_add(adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); 1077 1078 start = atop(bus_space_mmap(adev->memt, adev->gmc.aper_base, 0, 0, 0)); 1079 end = start + atop(adev->gmc.aper_size); 1080 uvm_page_physload(start, end, start, end, PHYSLOAD_DEVICE); 1081 #endif 1082 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1083 adev->gmc.mc_vram_size >> 20, 1084 (unsigned long long)adev->gmc.aper_size >> 20); 1085 DRM_INFO("RAM width %dbits %s\n", 1086 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1087 return amdgpu_ttm_init(adev); 1088 } 1089 1090 /** 1091 * amdgpu_bo_late_init - late init 1092 * @adev: amdgpu device object 1093 * 1094 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1095 * initialization. 1096 * 1097 * Returns: 1098 * 0 for success or a negative error code on failure. 1099 */ 1100 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1101 { 1102 amdgpu_ttm_late_init(adev); 1103 1104 return 0; 1105 } 1106 1107 /** 1108 * amdgpu_bo_fini - tear down memory manager 1109 * @adev: amdgpu device object 1110 * 1111 * Reverses amdgpu_bo_init() to tear down memory manager. 1112 */ 1113 void amdgpu_bo_fini(struct amdgpu_device *adev) 1114 { 1115 amdgpu_ttm_fini(adev); 1116 #ifdef __linux__ 1117 arch_phys_wc_del(adev->gmc.vram_mtrr); 1118 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1119 #else 1120 drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); 1121 #endif 1122 } 1123 1124 #ifdef notyet 1125 /** 1126 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1127 * @bo: &amdgpu_bo buffer object 1128 * @vma: vma as input from the fbdev mmap method 1129 * 1130 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1131 * 1132 * Returns: 1133 * 0 for success or a negative error code on failure. 1134 */ 1135 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1136 struct vm_area_struct *vma) 1137 { 1138 return ttm_fbdev_mmap(vma, &bo->tbo); 1139 } 1140 #endif 1141 1142 /** 1143 * amdgpu_bo_set_tiling_flags - set tiling flags 1144 * @bo: &amdgpu_bo buffer object 1145 * @tiling_flags: new flags 1146 * 1147 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1148 * kernel driver to set the tiling flags on a buffer. 1149 * 1150 * Returns: 1151 * 0 for success or a negative error code on failure. 1152 */ 1153 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1154 { 1155 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1156 1157 if (adev->family <= AMDGPU_FAMILY_CZ && 1158 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1159 return -EINVAL; 1160 1161 bo->tiling_flags = tiling_flags; 1162 return 0; 1163 } 1164 1165 /** 1166 * amdgpu_bo_get_tiling_flags - get tiling flags 1167 * @bo: &amdgpu_bo buffer object 1168 * @tiling_flags: returned flags 1169 * 1170 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1171 * set the tiling flags on a buffer. 1172 */ 1173 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1174 { 1175 lockdep_assert_held(&bo->tbo.resv->lock.base); 1176 1177 if (tiling_flags) 1178 *tiling_flags = bo->tiling_flags; 1179 } 1180 1181 /** 1182 * amdgpu_bo_set_metadata - set metadata 1183 * @bo: &amdgpu_bo buffer object 1184 * @metadata: new metadata 1185 * @metadata_size: size of the new metadata 1186 * @flags: flags of the new metadata 1187 * 1188 * Sets buffer object's metadata, its size and flags. 1189 * Used via GEM ioctl. 1190 * 1191 * Returns: 1192 * 0 for success or a negative error code on failure. 1193 */ 1194 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1195 uint32_t metadata_size, uint64_t flags) 1196 { 1197 void *buffer; 1198 1199 if (!metadata_size) { 1200 if (bo->metadata_size) { 1201 kfree(bo->metadata); 1202 bo->metadata = NULL; 1203 bo->metadata_size = 0; 1204 } 1205 return 0; 1206 } 1207 1208 if (metadata == NULL) 1209 return -EINVAL; 1210 1211 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1212 if (buffer == NULL) 1213 return -ENOMEM; 1214 1215 kfree(bo->metadata); 1216 bo->metadata_flags = flags; 1217 bo->metadata = buffer; 1218 bo->metadata_size = metadata_size; 1219 1220 return 0; 1221 } 1222 1223 /** 1224 * amdgpu_bo_get_metadata - get metadata 1225 * @bo: &amdgpu_bo buffer object 1226 * @buffer: returned metadata 1227 * @buffer_size: size of the buffer 1228 * @metadata_size: size of the returned metadata 1229 * @flags: flags of the returned metadata 1230 * 1231 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1232 * less than metadata_size. 1233 * Used via GEM ioctl. 1234 * 1235 * Returns: 1236 * 0 for success or a negative error code on failure. 1237 */ 1238 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1239 size_t buffer_size, uint32_t *metadata_size, 1240 uint64_t *flags) 1241 { 1242 if (!buffer && !metadata_size) 1243 return -EINVAL; 1244 1245 if (buffer) { 1246 if (buffer_size < bo->metadata_size) 1247 return -EINVAL; 1248 1249 if (bo->metadata_size) 1250 memcpy(buffer, bo->metadata, bo->metadata_size); 1251 } 1252 1253 if (metadata_size) 1254 *metadata_size = bo->metadata_size; 1255 if (flags) 1256 *flags = bo->metadata_flags; 1257 1258 return 0; 1259 } 1260 1261 /** 1262 * amdgpu_bo_move_notify - notification about a memory move 1263 * @bo: pointer to a buffer object 1264 * @evict: if this move is evicting the buffer from the graphics address space 1265 * @new_mem: new information of the bufer object 1266 * 1267 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1268 * bookkeeping. 1269 * TTM driver callback which is called when ttm moves a buffer. 1270 */ 1271 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1272 bool evict, 1273 struct ttm_mem_reg *new_mem) 1274 { 1275 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1276 struct amdgpu_bo *abo; 1277 struct ttm_mem_reg *old_mem = &bo->mem; 1278 1279 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1280 return; 1281 1282 abo = ttm_to_amdgpu_bo(bo); 1283 amdgpu_vm_bo_invalidate(adev, abo, evict); 1284 1285 amdgpu_bo_kunmap(abo); 1286 1287 /* remember the eviction */ 1288 if (evict) 1289 atomic64_inc(&adev->num_evictions); 1290 1291 /* update statistics */ 1292 if (!new_mem) 1293 return; 1294 1295 /* move_notify is called before move happens */ 1296 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1297 } 1298 1299 /** 1300 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1301 * @bo: pointer to a buffer object 1302 * 1303 * Notifies the driver we are taking a fault on this BO and have reserved it, 1304 * also performs bookkeeping. 1305 * TTM driver callback for dealing with vm faults. 1306 * 1307 * Returns: 1308 * 0 for success or a negative error code on failure. 1309 */ 1310 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1311 { 1312 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1313 struct ttm_operation_ctx ctx = { false, false }; 1314 struct amdgpu_bo *abo; 1315 unsigned long offset, size; 1316 int r; 1317 1318 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1319 return 0; 1320 1321 abo = ttm_to_amdgpu_bo(bo); 1322 1323 /* Remember that this BO was accessed by the CPU */ 1324 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1325 1326 if (bo->mem.mem_type != TTM_PL_VRAM) 1327 return 0; 1328 1329 size = bo->mem.num_pages << PAGE_SHIFT; 1330 offset = bo->mem.start << PAGE_SHIFT; 1331 if ((offset + size) <= adev->gmc.visible_vram_size) 1332 return 0; 1333 1334 /* Can't move a pinned BO to visible VRAM */ 1335 if (abo->pin_count > 0) 1336 return -EINVAL; 1337 1338 /* hurrah the memory is not visible ! */ 1339 atomic64_inc(&adev->num_vram_cpu_page_faults); 1340 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1341 AMDGPU_GEM_DOMAIN_GTT); 1342 1343 /* Avoid costly evictions; only set GTT as a busy placement */ 1344 abo->placement.num_busy_placement = 1; 1345 abo->placement.busy_placement = &abo->placements[1]; 1346 1347 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1348 if (unlikely(r != 0)) 1349 return r; 1350 1351 offset = bo->mem.start << PAGE_SHIFT; 1352 /* this should never happen */ 1353 if (bo->mem.mem_type == TTM_PL_VRAM && 1354 (offset + size) > adev->gmc.visible_vram_size) 1355 return -EINVAL; 1356 1357 return 0; 1358 } 1359 1360 /** 1361 * amdgpu_bo_fence - add fence to buffer object 1362 * 1363 * @bo: buffer object in question 1364 * @fence: fence to add 1365 * @shared: true if fence should be added shared 1366 * 1367 */ 1368 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1369 bool shared) 1370 { 1371 struct reservation_object *resv = bo->tbo.resv; 1372 1373 if (shared) 1374 reservation_object_add_shared_fence(resv, fence); 1375 else 1376 reservation_object_add_excl_fence(resv, fence); 1377 } 1378 1379 /** 1380 * amdgpu_bo_gpu_offset - return GPU offset of bo 1381 * @bo: amdgpu object for which we query the offset 1382 * 1383 * Note: object should either be pinned or reserved when calling this 1384 * function, it might be useful to add check for this for debugging. 1385 * 1386 * Returns: 1387 * current GPU offset of the object. 1388 */ 1389 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1390 { 1391 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1392 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT && 1393 !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem)); 1394 WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && 1395 !bo->pin_count); 1396 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1397 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1398 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1399 1400 return bo->tbo.offset; 1401 } 1402 1403 /** 1404 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1405 * @adev: amdgpu device object 1406 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1407 * 1408 * Returns: 1409 * Which of the allowed domains is preferred for pinning the BO for scanout. 1410 */ 1411 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1412 uint32_t domain) 1413 { 1414 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1415 domain = AMDGPU_GEM_DOMAIN_VRAM; 1416 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1417 domain = AMDGPU_GEM_DOMAIN_GTT; 1418 } 1419 return domain; 1420 } 1421