1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 #include "amdgpu_amdkfd.h" 40 41 /** 42 * DOC: amdgpu_object 43 * 44 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 45 * represents memory used by driver (VRAM, system memory, etc.). The driver 46 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 47 * to create/destroy/set buffer object which are then managed by the kernel TTM 48 * memory manager. 49 * The interfaces are also used internally by kernel clients, including gfx, 50 * uvd, etc. for kernel managed allocations used by the GPU. 51 * 52 */ 53 54 static bool amdgpu_bo_need_backup(struct amdgpu_device *adev) 55 { 56 if (adev->flags & AMD_IS_APU) 57 return false; 58 59 if (amdgpu_gpu_recovery == 0 || 60 (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev))) 61 return false; 62 63 return true; 64 } 65 66 /** 67 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 68 * 69 * @bo: &amdgpu_bo buffer object 70 * 71 * This function is called when a BO stops being pinned, and updates the 72 * &amdgpu_device pin_size values accordingly. 73 */ 74 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 75 { 76 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 77 78 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 79 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 80 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 81 &adev->visible_pin_size); 82 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 83 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 84 } 85 } 86 87 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 88 { 89 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 90 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 91 92 if (bo->pin_count > 0) 93 amdgpu_bo_subtract_pin_size(bo); 94 95 if (bo->kfd_bo) 96 amdgpu_amdkfd_unreserve_system_memory_limit(bo); 97 98 amdgpu_bo_kunmap(bo); 99 100 if (bo->gem_base.import_attach) 101 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg); 102 drm_gem_object_release(&bo->gem_base); 103 amdgpu_bo_unref(&bo->parent); 104 if (!list_empty(&bo->shadow_list)) { 105 mutex_lock(&adev->shadow_list_lock); 106 list_del_init(&bo->shadow_list); 107 mutex_unlock(&adev->shadow_list_lock); 108 } 109 kfree(bo->metadata); 110 pool_put(&bo->adev->ddev->objpl, bo); 111 } 112 113 /** 114 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 115 * @bo: buffer object to be checked 116 * 117 * Uses destroy function associated with the object to determine if this is 118 * an &amdgpu_bo. 119 * 120 * Returns: 121 * true if the object belongs to &amdgpu_bo, false if not. 122 */ 123 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 124 { 125 if (bo->destroy == &amdgpu_bo_destroy) 126 return true; 127 return false; 128 } 129 130 /** 131 * amdgpu_bo_placement_from_domain - set buffer's placement 132 * @abo: &amdgpu_bo buffer object whose placement is to be set 133 * @domain: requested domain 134 * 135 * Sets buffer's placement according to requested domain and the buffer's 136 * flags. 137 */ 138 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 139 { 140 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 141 struct ttm_placement *placement = &abo->placement; 142 struct ttm_place *places = abo->placements; 143 u64 flags = abo->flags; 144 u32 c = 0; 145 146 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 147 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 148 149 places[c].fpfn = 0; 150 places[c].lpfn = 0; 151 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 152 TTM_PL_FLAG_VRAM; 153 154 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 155 places[c].lpfn = visible_pfn; 156 else 157 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 158 159 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 160 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 161 c++; 162 } 163 164 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 165 places[c].fpfn = 0; 166 if (flags & AMDGPU_GEM_CREATE_SHADOW) 167 places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 168 else 169 places[c].lpfn = 0; 170 places[c].flags = TTM_PL_FLAG_TT; 171 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 172 places[c].flags |= TTM_PL_FLAG_WC | 173 TTM_PL_FLAG_UNCACHED; 174 else 175 places[c].flags |= TTM_PL_FLAG_CACHED; 176 c++; 177 } 178 179 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 180 places[c].fpfn = 0; 181 places[c].lpfn = 0; 182 places[c].flags = TTM_PL_FLAG_SYSTEM; 183 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 184 places[c].flags |= TTM_PL_FLAG_WC | 185 TTM_PL_FLAG_UNCACHED; 186 else 187 places[c].flags |= TTM_PL_FLAG_CACHED; 188 c++; 189 } 190 191 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 192 places[c].fpfn = 0; 193 places[c].lpfn = 0; 194 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 195 c++; 196 } 197 198 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 199 places[c].fpfn = 0; 200 places[c].lpfn = 0; 201 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 202 c++; 203 } 204 205 if (domain & AMDGPU_GEM_DOMAIN_OA) { 206 places[c].fpfn = 0; 207 places[c].lpfn = 0; 208 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 209 c++; 210 } 211 212 if (!c) { 213 places[c].fpfn = 0; 214 places[c].lpfn = 0; 215 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 216 c++; 217 } 218 219 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 220 221 placement->num_placement = c; 222 placement->placement = places; 223 224 placement->num_busy_placement = c; 225 placement->busy_placement = places; 226 } 227 228 /** 229 * amdgpu_bo_create_reserved - create reserved BO for kernel use 230 * 231 * @adev: amdgpu device object 232 * @size: size for the new BO 233 * @align: alignment for the new BO 234 * @domain: where to place it 235 * @bo_ptr: used to initialize BOs in structures 236 * @gpu_addr: GPU addr of the pinned BO 237 * @cpu_addr: optional CPU address mapping 238 * 239 * Allocates and pins a BO for kernel internal use, and returns it still 240 * reserved. 241 * 242 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 243 * 244 * Returns: 245 * 0 on success, negative error code otherwise. 246 */ 247 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 248 unsigned long size, int align, 249 u32 domain, struct amdgpu_bo **bo_ptr, 250 u64 *gpu_addr, void **cpu_addr) 251 { 252 struct amdgpu_bo_param bp; 253 bool free = false; 254 int r; 255 256 memset(&bp, 0, sizeof(bp)); 257 bp.size = size; 258 bp.byte_align = align; 259 bp.domain = domain; 260 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 261 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 262 bp.type = ttm_bo_type_kernel; 263 bp.resv = NULL; 264 265 if (!*bo_ptr) { 266 r = amdgpu_bo_create(adev, &bp, bo_ptr); 267 if (r) { 268 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 269 r); 270 return r; 271 } 272 free = true; 273 } 274 275 r = amdgpu_bo_reserve(*bo_ptr, false); 276 if (r) { 277 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 278 goto error_free; 279 } 280 281 r = amdgpu_bo_pin(*bo_ptr, domain); 282 if (r) { 283 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 284 goto error_unreserve; 285 } 286 287 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 288 if (r) { 289 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 290 goto error_unpin; 291 } 292 293 if (gpu_addr) 294 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 295 296 if (cpu_addr) { 297 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 298 if (r) { 299 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 300 goto error_unpin; 301 } 302 } 303 304 return 0; 305 306 error_unpin: 307 amdgpu_bo_unpin(*bo_ptr); 308 error_unreserve: 309 amdgpu_bo_unreserve(*bo_ptr); 310 311 error_free: 312 if (free) 313 amdgpu_bo_unref(bo_ptr); 314 315 return r; 316 } 317 318 /** 319 * amdgpu_bo_create_kernel - create BO for kernel use 320 * 321 * @adev: amdgpu device object 322 * @size: size for the new BO 323 * @align: alignment for the new BO 324 * @domain: where to place it 325 * @bo_ptr: used to initialize BOs in structures 326 * @gpu_addr: GPU addr of the pinned BO 327 * @cpu_addr: optional CPU address mapping 328 * 329 * Allocates and pins a BO for kernel internal use. 330 * 331 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 332 * 333 * Returns: 334 * 0 on success, negative error code otherwise. 335 */ 336 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 337 unsigned long size, int align, 338 u32 domain, struct amdgpu_bo **bo_ptr, 339 u64 *gpu_addr, void **cpu_addr) 340 { 341 int r; 342 343 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 344 gpu_addr, cpu_addr); 345 346 if (r) 347 return r; 348 349 amdgpu_bo_unreserve(*bo_ptr); 350 351 return 0; 352 } 353 354 /** 355 * amdgpu_bo_free_kernel - free BO for kernel use 356 * 357 * @bo: amdgpu BO to free 358 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 359 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 360 * 361 * unmaps and unpin a BO for kernel internal use. 362 */ 363 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 364 void **cpu_addr) 365 { 366 if (*bo == NULL) 367 return; 368 369 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 370 if (cpu_addr) 371 amdgpu_bo_kunmap(*bo); 372 373 amdgpu_bo_unpin(*bo); 374 amdgpu_bo_unreserve(*bo); 375 } 376 amdgpu_bo_unref(bo); 377 378 if (gpu_addr) 379 *gpu_addr = 0; 380 381 if (cpu_addr) 382 *cpu_addr = NULL; 383 } 384 385 /* Validate bo size is bit bigger then the request domain */ 386 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 387 unsigned long size, u32 domain) 388 { 389 struct ttm_mem_type_manager *man = NULL; 390 391 /* 392 * If GTT is part of requested domains the check must succeed to 393 * allow fall back to GTT 394 */ 395 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 396 man = &adev->mman.bdev.man[TTM_PL_TT]; 397 398 if (size < (man->size << PAGE_SHIFT)) 399 return true; 400 else 401 goto fail; 402 } 403 404 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 405 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 406 407 if (size < (man->size << PAGE_SHIFT)) 408 return true; 409 else 410 goto fail; 411 } 412 413 414 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 415 return true; 416 417 fail: 418 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 419 man->size << PAGE_SHIFT); 420 return false; 421 } 422 423 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 424 struct amdgpu_bo_param *bp, 425 struct amdgpu_bo **bo_ptr) 426 { 427 struct ttm_operation_ctx ctx = { 428 .interruptible = (bp->type != ttm_bo_type_kernel), 429 .no_wait_gpu = false, 430 .resv = bp->resv, 431 .flags = bp->type != ttm_bo_type_kernel ? 432 TTM_OPT_FLAG_ALLOW_RES_EVICT : 0 433 }; 434 struct amdgpu_bo *bo; 435 unsigned long page_align, size = bp->size; 436 size_t acc_size; 437 int r; 438 439 page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 440 size = roundup2(size, PAGE_SIZE); 441 442 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 443 return -ENOMEM; 444 445 *bo_ptr = NULL; 446 447 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 448 sizeof(struct amdgpu_bo)); 449 450 bo = pool_get(&adev->ddev->objpl, PR_WAITOK | PR_ZERO); 451 if (bo == NULL) 452 return -ENOMEM; 453 drm_gem_private_object_init(adev->ddev, &bo->gem_base, size); 454 bo->adev = adev; 455 INIT_LIST_HEAD(&bo->shadow_list); 456 INIT_LIST_HEAD(&bo->va); 457 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 458 bp->domain; 459 bo->allowed_domains = bo->preferred_domains; 460 if (bp->type != ttm_bo_type_kernel && 461 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 462 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 463 464 bo->flags = bp->flags; 465 466 #ifdef CONFIG_X86_32 467 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 468 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 469 */ 470 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 471 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 472 /* Don't try to enable write-combining when it can't work, or things 473 * may be slow 474 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 475 */ 476 477 #ifndef CONFIG_COMPILE_TEST 478 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 479 thanks to write-combining 480 #endif 481 482 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 483 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 484 "better performance thanks to write-combining\n"); 485 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 486 #else 487 /* For architectures that don't support WC memory, 488 * mask out the WC flag from the BO 489 */ 490 if (!drm_arch_can_wc_memory()) 491 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 492 #endif 493 494 bo->tbo.bdev = &adev->mman.bdev; 495 amdgpu_bo_placement_from_domain(bo, bp->domain); 496 if (bp->type == ttm_bo_type_kernel) 497 bo->tbo.priority = 1; 498 499 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 500 &bo->placement, page_align, &ctx, acc_size, 501 NULL, bp->resv, &amdgpu_bo_destroy); 502 if (unlikely(r != 0)) 503 return r; 504 505 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 506 bo->tbo.mem.mem_type == TTM_PL_VRAM && 507 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 508 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 509 ctx.bytes_moved); 510 else 511 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 512 513 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 514 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 515 struct dma_fence *fence; 516 517 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); 518 if (unlikely(r)) 519 goto fail_unreserve; 520 521 amdgpu_bo_fence(bo, fence, false); 522 dma_fence_put(bo->tbo.moving); 523 bo->tbo.moving = dma_fence_get(fence); 524 dma_fence_put(fence); 525 } 526 if (!bp->resv) 527 amdgpu_bo_unreserve(bo); 528 *bo_ptr = bo; 529 530 trace_amdgpu_bo_create(bo); 531 532 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 533 if (bp->type == ttm_bo_type_device) 534 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 535 536 return 0; 537 538 fail_unreserve: 539 if (!bp->resv) 540 ww_mutex_unlock(&bo->tbo.resv->lock); 541 amdgpu_bo_unref(&bo); 542 return r; 543 } 544 545 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 546 unsigned long size, int byte_align, 547 struct amdgpu_bo *bo) 548 { 549 struct amdgpu_bo_param bp; 550 int r; 551 552 if (bo->shadow) 553 return 0; 554 555 memset(&bp, 0, sizeof(bp)); 556 bp.size = size; 557 bp.byte_align = byte_align; 558 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 559 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 560 AMDGPU_GEM_CREATE_SHADOW; 561 bp.type = ttm_bo_type_kernel; 562 bp.resv = bo->tbo.resv; 563 564 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 565 if (!r) { 566 bo->shadow->parent = amdgpu_bo_ref(bo); 567 mutex_lock(&adev->shadow_list_lock); 568 list_add_tail(&bo->shadow_list, &adev->shadow_list); 569 mutex_unlock(&adev->shadow_list_lock); 570 } 571 572 return r; 573 } 574 575 /** 576 * amdgpu_bo_create - create an &amdgpu_bo buffer object 577 * @adev: amdgpu device object 578 * @bp: parameters to be used for the buffer object 579 * @bo_ptr: pointer to the buffer object pointer 580 * 581 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 582 * shadow object. 583 * Shadow object is used to backup the original buffer object, and is always 584 * in GTT. 585 * 586 * Returns: 587 * 0 for success or a negative error code on failure. 588 */ 589 int amdgpu_bo_create(struct amdgpu_device *adev, 590 struct amdgpu_bo_param *bp, 591 struct amdgpu_bo **bo_ptr) 592 { 593 u64 flags = bp->flags; 594 int r; 595 596 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 597 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 598 if (r) 599 return r; 600 601 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_bo_need_backup(adev)) { 602 if (!bp->resv) 603 WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv, 604 NULL)); 605 606 r = amdgpu_bo_create_shadow(adev, bp->size, bp->byte_align, (*bo_ptr)); 607 608 if (!bp->resv) 609 reservation_object_unlock((*bo_ptr)->tbo.resv); 610 611 if (r) 612 amdgpu_bo_unref(bo_ptr); 613 } 614 615 return r; 616 } 617 618 /** 619 * amdgpu_bo_backup_to_shadow - Backs up an &amdgpu_bo buffer object 620 * @adev: amdgpu device object 621 * @ring: amdgpu_ring for the engine handling the buffer operations 622 * @bo: &amdgpu_bo buffer to be backed up 623 * @resv: reservation object with embedded fence 624 * @fence: dma_fence associated with the operation 625 * @direct: whether to submit the job directly 626 * 627 * Copies an &amdgpu_bo buffer object to its shadow object. 628 * Not used for now. 629 * 630 * Returns: 631 * 0 for success or a negative error code on failure. 632 */ 633 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, 634 struct amdgpu_ring *ring, 635 struct amdgpu_bo *bo, 636 struct reservation_object *resv, 637 struct dma_fence **fence, 638 bool direct) 639 640 { 641 struct amdgpu_bo *shadow = bo->shadow; 642 uint64_t bo_addr, shadow_addr; 643 int r; 644 645 if (!shadow) 646 return -EINVAL; 647 648 bo_addr = amdgpu_bo_gpu_offset(bo); 649 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 650 651 r = reservation_object_reserve_shared(bo->tbo.resv); 652 if (r) 653 goto err; 654 655 r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr, 656 amdgpu_bo_size(bo), resv, fence, 657 direct, false); 658 if (!r) 659 amdgpu_bo_fence(bo, *fence, true); 660 661 err: 662 return r; 663 } 664 665 /** 666 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 667 * @bo: pointer to the buffer object 668 * 669 * Sets placement according to domain; and changes placement and caching 670 * policy of the buffer object according to the placement. 671 * This is used for validating shadow bos. It calls ttm_bo_validate() to 672 * make sure the buffer is resident where it needs to be. 673 * 674 * Returns: 675 * 0 for success or a negative error code on failure. 676 */ 677 int amdgpu_bo_validate(struct amdgpu_bo *bo) 678 { 679 struct ttm_operation_ctx ctx = { false, false }; 680 uint32_t domain; 681 int r; 682 683 if (bo->pin_count) 684 return 0; 685 686 domain = bo->preferred_domains; 687 688 retry: 689 amdgpu_bo_placement_from_domain(bo, domain); 690 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 691 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 692 domain = bo->allowed_domains; 693 goto retry; 694 } 695 696 return r; 697 } 698 699 /** 700 * amdgpu_bo_restore_from_shadow - restore an &amdgpu_bo buffer object 701 * @adev: amdgpu device object 702 * @ring: amdgpu_ring for the engine handling the buffer operations 703 * @bo: &amdgpu_bo buffer to be restored 704 * @resv: reservation object with embedded fence 705 * @fence: dma_fence associated with the operation 706 * @direct: whether to submit the job directly 707 * 708 * Copies a buffer object's shadow content back to the object. 709 * This is used for recovering a buffer from its shadow in case of a gpu 710 * reset where vram context may be lost. 711 * 712 * Returns: 713 * 0 for success or a negative error code on failure. 714 */ 715 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, 716 struct amdgpu_ring *ring, 717 struct amdgpu_bo *bo, 718 struct reservation_object *resv, 719 struct dma_fence **fence, 720 bool direct) 721 722 { 723 struct amdgpu_bo *shadow = bo->shadow; 724 uint64_t bo_addr, shadow_addr; 725 int r; 726 727 if (!shadow) 728 return -EINVAL; 729 730 bo_addr = amdgpu_bo_gpu_offset(bo); 731 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow); 732 733 r = reservation_object_reserve_shared(bo->tbo.resv); 734 if (r) 735 goto err; 736 737 r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr, 738 amdgpu_bo_size(bo), resv, fence, 739 direct, false); 740 if (!r) 741 amdgpu_bo_fence(bo, *fence, true); 742 743 err: 744 return r; 745 } 746 747 /** 748 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 749 * @bo: &amdgpu_bo buffer object to be mapped 750 * @ptr: kernel virtual address to be returned 751 * 752 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 753 * amdgpu_bo_kptr() to get the kernel virtual address. 754 * 755 * Returns: 756 * 0 for success or a negative error code on failure. 757 */ 758 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 759 { 760 void *kptr; 761 long r; 762 763 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 764 return -EPERM; 765 766 kptr = amdgpu_bo_kptr(bo); 767 if (kptr) { 768 if (ptr) 769 *ptr = kptr; 770 return 0; 771 } 772 773 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false, 774 MAX_SCHEDULE_TIMEOUT); 775 if (r < 0) 776 return r; 777 778 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 779 if (r) 780 return r; 781 782 if (ptr) 783 *ptr = amdgpu_bo_kptr(bo); 784 785 return 0; 786 } 787 788 /** 789 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 790 * @bo: &amdgpu_bo buffer object 791 * 792 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 793 * 794 * Returns: 795 * the virtual address of a buffer object area. 796 */ 797 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 798 { 799 bool is_iomem; 800 801 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 802 } 803 804 /** 805 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 806 * @bo: &amdgpu_bo buffer object to be unmapped 807 * 808 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 809 */ 810 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 811 { 812 if (bo->kmap.bo) 813 ttm_bo_kunmap(&bo->kmap); 814 } 815 816 /** 817 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 818 * @bo: &amdgpu_bo buffer object 819 * 820 * References the contained &ttm_buffer_object. 821 * 822 * Returns: 823 * a refcounted pointer to the &amdgpu_bo buffer object. 824 */ 825 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 826 { 827 if (bo == NULL) 828 return NULL; 829 830 ttm_bo_get(&bo->tbo); 831 return bo; 832 } 833 834 /** 835 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 836 * @bo: &amdgpu_bo buffer object 837 * 838 * Unreferences the contained &ttm_buffer_object and clear the pointer 839 */ 840 void amdgpu_bo_unref(struct amdgpu_bo **bo) 841 { 842 struct ttm_buffer_object *tbo; 843 844 if ((*bo) == NULL) 845 return; 846 847 tbo = &((*bo)->tbo); 848 ttm_bo_put(tbo); 849 *bo = NULL; 850 } 851 852 /** 853 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 854 * @bo: &amdgpu_bo buffer object to be pinned 855 * @domain: domain to be pinned to 856 * @min_offset: the start of requested address range 857 * @max_offset: the end of requested address range 858 * 859 * Pins the buffer object according to requested domain and address range. If 860 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 861 * pin_count and pin_size accordingly. 862 * 863 * Pinning means to lock pages in memory along with keeping them at a fixed 864 * offset. It is required when a buffer can not be moved, for example, when 865 * a display buffer is being scanned out. 866 * 867 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 868 * where to pin a buffer if there are specific restrictions on where a buffer 869 * must be located. 870 * 871 * Returns: 872 * 0 for success or a negative error code on failure. 873 */ 874 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 875 u64 min_offset, u64 max_offset) 876 { 877 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 878 struct ttm_operation_ctx ctx = { false, false }; 879 int r, i; 880 881 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 882 return -EPERM; 883 884 if (WARN_ON_ONCE(min_offset > max_offset)) 885 return -EINVAL; 886 887 /* A shared bo cannot be migrated to VRAM */ 888 if (bo->prime_shared_count) { 889 if (domain & AMDGPU_GEM_DOMAIN_GTT) 890 domain = AMDGPU_GEM_DOMAIN_GTT; 891 else 892 return -EINVAL; 893 } 894 895 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 896 * See function amdgpu_display_supported_domains() 897 */ 898 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 899 900 if (bo->pin_count) { 901 uint32_t mem_type = bo->tbo.mem.mem_type; 902 903 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 904 return -EINVAL; 905 906 bo->pin_count++; 907 908 if (max_offset != 0) { 909 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 910 WARN_ON_ONCE(max_offset < 911 (amdgpu_bo_gpu_offset(bo) - domain_start)); 912 } 913 914 return 0; 915 } 916 917 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 918 /* force to pin into visible video ram */ 919 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 920 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 921 amdgpu_bo_placement_from_domain(bo, domain); 922 for (i = 0; i < bo->placement.num_placement; i++) { 923 unsigned fpfn, lpfn; 924 925 fpfn = min_offset >> PAGE_SHIFT; 926 lpfn = max_offset >> PAGE_SHIFT; 927 928 if (fpfn > bo->placements[i].fpfn) 929 bo->placements[i].fpfn = fpfn; 930 if (!bo->placements[i].lpfn || 931 (lpfn && lpfn < bo->placements[i].lpfn)) 932 bo->placements[i].lpfn = lpfn; 933 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 934 } 935 936 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 937 if (unlikely(r)) { 938 dev_err(adev->dev, "%p pin failed\n", bo); 939 goto error; 940 } 941 942 bo->pin_count = 1; 943 944 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 945 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 946 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 947 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 948 &adev->visible_pin_size); 949 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 950 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 951 } 952 953 error: 954 return r; 955 } 956 957 /** 958 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 959 * @bo: &amdgpu_bo buffer object to be pinned 960 * @domain: domain to be pinned to 961 * 962 * A simple wrapper to amdgpu_bo_pin_restricted(). 963 * Provides a simpler API for buffers that do not have any strict restrictions 964 * on where a buffer must be located. 965 * 966 * Returns: 967 * 0 for success or a negative error code on failure. 968 */ 969 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 970 { 971 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 972 } 973 974 /** 975 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 976 * @bo: &amdgpu_bo buffer object to be unpinned 977 * 978 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 979 * Changes placement and pin size accordingly. 980 * 981 * Returns: 982 * 0 for success or a negative error code on failure. 983 */ 984 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 985 { 986 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 987 struct ttm_operation_ctx ctx = { false, false }; 988 int r, i; 989 990 if (!bo->pin_count) { 991 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 992 return 0; 993 } 994 bo->pin_count--; 995 if (bo->pin_count) 996 return 0; 997 998 amdgpu_bo_subtract_pin_size(bo); 999 1000 for (i = 0; i < bo->placement.num_placement; i++) { 1001 bo->placements[i].lpfn = 0; 1002 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 1003 } 1004 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1005 if (unlikely(r)) 1006 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 1007 1008 return r; 1009 } 1010 1011 /** 1012 * amdgpu_bo_evict_vram - evict VRAM buffers 1013 * @adev: amdgpu device object 1014 * 1015 * Evicts all VRAM buffers on the lru list of the memory type. 1016 * Mainly used for evicting vram at suspend time. 1017 * 1018 * Returns: 1019 * 0 for success or a negative error code on failure. 1020 */ 1021 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 1022 { 1023 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 1024 if (0 && (adev->flags & AMD_IS_APU)) { 1025 /* Useless to evict on IGP chips */ 1026 return 0; 1027 } 1028 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 1029 } 1030 1031 static const char *amdgpu_vram_names[] = { 1032 "UNKNOWN", 1033 "GDDR1", 1034 "DDR2", 1035 "GDDR3", 1036 "GDDR4", 1037 "GDDR5", 1038 "HBM", 1039 "DDR3", 1040 "DDR4", 1041 }; 1042 1043 /** 1044 * amdgpu_bo_init - initialize memory manager 1045 * @adev: amdgpu device object 1046 * 1047 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1048 * 1049 * Returns: 1050 * 0 for success or a negative error code on failure. 1051 */ 1052 int amdgpu_bo_init(struct amdgpu_device *adev) 1053 { 1054 paddr_t start, end; 1055 1056 #ifdef __linux__ 1057 /* reserve PAT memory space to WC for VRAM */ 1058 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1059 adev->gmc.aper_size); 1060 1061 /* Add an MTRR for the VRAM */ 1062 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1063 adev->gmc.aper_size); 1064 #else 1065 drm_mtrr_add(adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); 1066 1067 start = atop(bus_space_mmap(adev->memt, adev->gmc.aper_base, 0, 0, 0)); 1068 end = start + atop(adev->gmc.aper_size); 1069 uvm_page_physload(start, end, start, end, PHYSLOAD_DEVICE); 1070 #endif 1071 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1072 adev->gmc.mc_vram_size >> 20, 1073 (unsigned long long)adev->gmc.aper_size >> 20); 1074 DRM_INFO("RAM width %dbits %s\n", 1075 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1076 return amdgpu_ttm_init(adev); 1077 } 1078 1079 /** 1080 * amdgpu_bo_late_init - late init 1081 * @adev: amdgpu device object 1082 * 1083 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1084 * initialization. 1085 * 1086 * Returns: 1087 * 0 for success or a negative error code on failure. 1088 */ 1089 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1090 { 1091 amdgpu_ttm_late_init(adev); 1092 1093 return 0; 1094 } 1095 1096 /** 1097 * amdgpu_bo_fini - tear down memory manager 1098 * @adev: amdgpu device object 1099 * 1100 * Reverses amdgpu_bo_init() to tear down memory manager. 1101 */ 1102 void amdgpu_bo_fini(struct amdgpu_device *adev) 1103 { 1104 amdgpu_ttm_fini(adev); 1105 #ifdef __linux__ 1106 arch_phys_wc_del(adev->gmc.vram_mtrr); 1107 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1108 #else 1109 drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); 1110 #endif 1111 } 1112 1113 #ifdef notyet 1114 /** 1115 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1116 * @bo: &amdgpu_bo buffer object 1117 * @vma: vma as input from the fbdev mmap method 1118 * 1119 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1120 * 1121 * Returns: 1122 * 0 for success or a negative error code on failure. 1123 */ 1124 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1125 struct vm_area_struct *vma) 1126 { 1127 return ttm_fbdev_mmap(vma, &bo->tbo); 1128 } 1129 #endif 1130 1131 /** 1132 * amdgpu_bo_set_tiling_flags - set tiling flags 1133 * @bo: &amdgpu_bo buffer object 1134 * @tiling_flags: new flags 1135 * 1136 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1137 * kernel driver to set the tiling flags on a buffer. 1138 * 1139 * Returns: 1140 * 0 for success or a negative error code on failure. 1141 */ 1142 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1143 { 1144 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1145 1146 if (adev->family <= AMDGPU_FAMILY_CZ && 1147 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1148 return -EINVAL; 1149 1150 bo->tiling_flags = tiling_flags; 1151 return 0; 1152 } 1153 1154 /** 1155 * amdgpu_bo_get_tiling_flags - get tiling flags 1156 * @bo: &amdgpu_bo buffer object 1157 * @tiling_flags: returned flags 1158 * 1159 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1160 * set the tiling flags on a buffer. 1161 */ 1162 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1163 { 1164 lockdep_assert_held(&bo->tbo.resv->lock.base); 1165 1166 if (tiling_flags) 1167 *tiling_flags = bo->tiling_flags; 1168 } 1169 1170 /** 1171 * amdgpu_bo_set_metadata - set metadata 1172 * @bo: &amdgpu_bo buffer object 1173 * @metadata: new metadata 1174 * @metadata_size: size of the new metadata 1175 * @flags: flags of the new metadata 1176 * 1177 * Sets buffer object's metadata, its size and flags. 1178 * Used via GEM ioctl. 1179 * 1180 * Returns: 1181 * 0 for success or a negative error code on failure. 1182 */ 1183 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1184 uint32_t metadata_size, uint64_t flags) 1185 { 1186 void *buffer; 1187 1188 if (!metadata_size) { 1189 if (bo->metadata_size) { 1190 kfree(bo->metadata); 1191 bo->metadata = NULL; 1192 bo->metadata_size = 0; 1193 } 1194 return 0; 1195 } 1196 1197 if (metadata == NULL) 1198 return -EINVAL; 1199 1200 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1201 if (buffer == NULL) 1202 return -ENOMEM; 1203 1204 kfree(bo->metadata); 1205 bo->metadata_flags = flags; 1206 bo->metadata = buffer; 1207 bo->metadata_size = metadata_size; 1208 1209 return 0; 1210 } 1211 1212 /** 1213 * amdgpu_bo_get_metadata - get metadata 1214 * @bo: &amdgpu_bo buffer object 1215 * @buffer: returned metadata 1216 * @buffer_size: size of the buffer 1217 * @metadata_size: size of the returned metadata 1218 * @flags: flags of the returned metadata 1219 * 1220 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1221 * less than metadata_size. 1222 * Used via GEM ioctl. 1223 * 1224 * Returns: 1225 * 0 for success or a negative error code on failure. 1226 */ 1227 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1228 size_t buffer_size, uint32_t *metadata_size, 1229 uint64_t *flags) 1230 { 1231 if (!buffer && !metadata_size) 1232 return -EINVAL; 1233 1234 if (buffer) { 1235 if (buffer_size < bo->metadata_size) 1236 return -EINVAL; 1237 1238 if (bo->metadata_size) 1239 memcpy(buffer, bo->metadata, bo->metadata_size); 1240 } 1241 1242 if (metadata_size) 1243 *metadata_size = bo->metadata_size; 1244 if (flags) 1245 *flags = bo->metadata_flags; 1246 1247 return 0; 1248 } 1249 1250 /** 1251 * amdgpu_bo_move_notify - notification about a memory move 1252 * @bo: pointer to a buffer object 1253 * @evict: if this move is evicting the buffer from the graphics address space 1254 * @new_mem: new information of the bufer object 1255 * 1256 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1257 * bookkeeping. 1258 * TTM driver callback which is called when ttm moves a buffer. 1259 */ 1260 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1261 bool evict, 1262 struct ttm_mem_reg *new_mem) 1263 { 1264 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1265 struct amdgpu_bo *abo; 1266 struct ttm_mem_reg *old_mem = &bo->mem; 1267 1268 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1269 return; 1270 1271 abo = ttm_to_amdgpu_bo(bo); 1272 amdgpu_vm_bo_invalidate(adev, abo, evict); 1273 1274 amdgpu_bo_kunmap(abo); 1275 1276 /* remember the eviction */ 1277 if (evict) 1278 atomic64_inc(&adev->num_evictions); 1279 1280 /* update statistics */ 1281 if (!new_mem) 1282 return; 1283 1284 /* move_notify is called before move happens */ 1285 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1286 } 1287 1288 /** 1289 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1290 * @bo: pointer to a buffer object 1291 * 1292 * Notifies the driver we are taking a fault on this BO and have reserved it, 1293 * also performs bookkeeping. 1294 * TTM driver callback for dealing with vm faults. 1295 * 1296 * Returns: 1297 * 0 for success or a negative error code on failure. 1298 */ 1299 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1300 { 1301 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1302 struct ttm_operation_ctx ctx = { false, false }; 1303 struct amdgpu_bo *abo; 1304 unsigned long offset, size; 1305 int r; 1306 1307 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1308 return 0; 1309 1310 abo = ttm_to_amdgpu_bo(bo); 1311 1312 /* Remember that this BO was accessed by the CPU */ 1313 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1314 1315 if (bo->mem.mem_type != TTM_PL_VRAM) 1316 return 0; 1317 1318 size = bo->mem.num_pages << PAGE_SHIFT; 1319 offset = bo->mem.start << PAGE_SHIFT; 1320 if ((offset + size) <= adev->gmc.visible_vram_size) 1321 return 0; 1322 1323 /* Can't move a pinned BO to visible VRAM */ 1324 if (abo->pin_count > 0) 1325 return -EINVAL; 1326 1327 /* hurrah the memory is not visible ! */ 1328 atomic64_inc(&adev->num_vram_cpu_page_faults); 1329 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1330 AMDGPU_GEM_DOMAIN_GTT); 1331 1332 /* Avoid costly evictions; only set GTT as a busy placement */ 1333 abo->placement.num_busy_placement = 1; 1334 abo->placement.busy_placement = &abo->placements[1]; 1335 1336 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1337 if (unlikely(r != 0)) 1338 return r; 1339 1340 offset = bo->mem.start << PAGE_SHIFT; 1341 /* this should never happen */ 1342 if (bo->mem.mem_type == TTM_PL_VRAM && 1343 (offset + size) > adev->gmc.visible_vram_size) 1344 return -EINVAL; 1345 1346 return 0; 1347 } 1348 1349 /** 1350 * amdgpu_bo_fence - add fence to buffer object 1351 * 1352 * @bo: buffer object in question 1353 * @fence: fence to add 1354 * @shared: true if fence should be added shared 1355 * 1356 */ 1357 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1358 bool shared) 1359 { 1360 struct reservation_object *resv = bo->tbo.resv; 1361 1362 if (shared) 1363 reservation_object_add_shared_fence(resv, fence); 1364 else 1365 reservation_object_add_excl_fence(resv, fence); 1366 } 1367 1368 /** 1369 * amdgpu_bo_gpu_offset - return GPU offset of bo 1370 * @bo: amdgpu object for which we query the offset 1371 * 1372 * Note: object should either be pinned or reserved when calling this 1373 * function, it might be useful to add check for this for debugging. 1374 * 1375 * Returns: 1376 * current GPU offset of the object. 1377 */ 1378 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1379 { 1380 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1381 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT && 1382 !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem)); 1383 WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && 1384 !bo->pin_count); 1385 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1386 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1387 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1388 1389 return bo->tbo.offset; 1390 } 1391 1392 /** 1393 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1394 * @adev: amdgpu device object 1395 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1396 * 1397 * Returns: 1398 * Which of the allowed domains is preferred for pinning the BO for scanout. 1399 */ 1400 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1401 uint32_t domain) 1402 { 1403 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1404 domain = AMDGPU_GEM_DOMAIN_VRAM; 1405 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1406 domain = AMDGPU_GEM_DOMAIN_GTT; 1407 } 1408 return domain; 1409 } 1410