1*1bb76ff1Sjsg /* 2*1bb76ff1Sjsg * Copyright 2022 Advanced Micro Devices, Inc. 3*1bb76ff1Sjsg * 4*1bb76ff1Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*1bb76ff1Sjsg * copy of this software and associated documentation files (the "Software"), 6*1bb76ff1Sjsg * to deal in the Software without restriction, including without limitation 7*1bb76ff1Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*1bb76ff1Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*1bb76ff1Sjsg * Software is furnished to do so, subject to the following conditions: 10*1bb76ff1Sjsg * 11*1bb76ff1Sjsg * The above copyright notice and this permission notice shall be included in 12*1bb76ff1Sjsg * all copies or substantial portions of the Software. 13*1bb76ff1Sjsg * 14*1bb76ff1Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*1bb76ff1Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*1bb76ff1Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*1bb76ff1Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*1bb76ff1Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*1bb76ff1Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*1bb76ff1Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*1bb76ff1Sjsg * 22*1bb76ff1Sjsg */ 23*1bb76ff1Sjsg 24*1bb76ff1Sjsg #ifndef __AMDGPU_LSDMA_H__ 25*1bb76ff1Sjsg #define __AMDGPU_LSDMA_H__ 26*1bb76ff1Sjsg 27*1bb76ff1Sjsg struct amdgpu_lsdma { 28*1bb76ff1Sjsg const struct amdgpu_lsdma_funcs *funcs; 29*1bb76ff1Sjsg }; 30*1bb76ff1Sjsg 31*1bb76ff1Sjsg struct amdgpu_lsdma_funcs { 32*1bb76ff1Sjsg int (*copy_mem)(struct amdgpu_device *adev, uint64_t src_addr, 33*1bb76ff1Sjsg uint64_t dst_addr, uint64_t size); 34*1bb76ff1Sjsg int (*fill_mem)(struct amdgpu_device *adev, uint64_t dst_addr, 35*1bb76ff1Sjsg uint32_t data, uint64_t size); 36*1bb76ff1Sjsg void (*update_memory_power_gating)(struct amdgpu_device *adev, bool enable); 37*1bb76ff1Sjsg }; 38*1bb76ff1Sjsg 39*1bb76ff1Sjsg int amdgpu_lsdma_copy_mem(struct amdgpu_device *adev, uint64_t src_addr, 40*1bb76ff1Sjsg uint64_t dst_addr, uint64_t mem_size); 41*1bb76ff1Sjsg int amdgpu_lsdma_fill_mem(struct amdgpu_device *adev, uint64_t dst_addr, 42*1bb76ff1Sjsg uint32_t data, uint64_t mem_size); 43*1bb76ff1Sjsg int amdgpu_lsdma_wait_for(struct amdgpu_device *adev, uint32_t reg_index, 44*1bb76ff1Sjsg uint32_t reg_val, uint32_t mask); 45*1bb76ff1Sjsg 46*1bb76ff1Sjsg #endif 47