1*1bb76ff1Sjsg /*
2*1bb76ff1Sjsg * Copyright 2022 Advanced Micro Devices, Inc.
3*1bb76ff1Sjsg *
4*1bb76ff1Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5*1bb76ff1Sjsg * copy of this software and associated documentation files (the "Software"),
6*1bb76ff1Sjsg * to deal in the Software without restriction, including without limitation
7*1bb76ff1Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*1bb76ff1Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9*1bb76ff1Sjsg * Software is furnished to do so, subject to the following conditions:
10*1bb76ff1Sjsg *
11*1bb76ff1Sjsg * The above copyright notice and this permission notice shall be included in
12*1bb76ff1Sjsg * all copies or substantial portions of the Software.
13*1bb76ff1Sjsg *
14*1bb76ff1Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*1bb76ff1Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*1bb76ff1Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*1bb76ff1Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*1bb76ff1Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*1bb76ff1Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*1bb76ff1Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21*1bb76ff1Sjsg *
22*1bb76ff1Sjsg */
23*1bb76ff1Sjsg
24*1bb76ff1Sjsg #include "amdgpu.h"
25*1bb76ff1Sjsg #include "amdgpu_lsdma.h"
26*1bb76ff1Sjsg
27*1bb76ff1Sjsg #define AMDGPU_LSDMA_MAX_SIZE 0x2000000ULL
28*1bb76ff1Sjsg
amdgpu_lsdma_wait_for(struct amdgpu_device * adev,uint32_t reg_index,uint32_t reg_val,uint32_t mask)29*1bb76ff1Sjsg int amdgpu_lsdma_wait_for(struct amdgpu_device *adev,
30*1bb76ff1Sjsg uint32_t reg_index, uint32_t reg_val,
31*1bb76ff1Sjsg uint32_t mask)
32*1bb76ff1Sjsg {
33*1bb76ff1Sjsg uint32_t val;
34*1bb76ff1Sjsg int i;
35*1bb76ff1Sjsg
36*1bb76ff1Sjsg for (i = 0; i < adev->usec_timeout; i++) {
37*1bb76ff1Sjsg val = RREG32(reg_index);
38*1bb76ff1Sjsg if ((val & mask) == reg_val)
39*1bb76ff1Sjsg return 0;
40*1bb76ff1Sjsg udelay(1);
41*1bb76ff1Sjsg }
42*1bb76ff1Sjsg
43*1bb76ff1Sjsg return -ETIME;
44*1bb76ff1Sjsg }
45*1bb76ff1Sjsg
amdgpu_lsdma_copy_mem(struct amdgpu_device * adev,uint64_t src_addr,uint64_t dst_addr,uint64_t mem_size)46*1bb76ff1Sjsg int amdgpu_lsdma_copy_mem(struct amdgpu_device *adev,
47*1bb76ff1Sjsg uint64_t src_addr,
48*1bb76ff1Sjsg uint64_t dst_addr,
49*1bb76ff1Sjsg uint64_t mem_size)
50*1bb76ff1Sjsg {
51*1bb76ff1Sjsg int ret;
52*1bb76ff1Sjsg
53*1bb76ff1Sjsg if (mem_size == 0)
54*1bb76ff1Sjsg return -EINVAL;
55*1bb76ff1Sjsg
56*1bb76ff1Sjsg while (mem_size > 0) {
57*1bb76ff1Sjsg uint64_t current_copy_size = min(mem_size, AMDGPU_LSDMA_MAX_SIZE);
58*1bb76ff1Sjsg
59*1bb76ff1Sjsg ret = adev->lsdma.funcs->copy_mem(adev, src_addr, dst_addr, current_copy_size);
60*1bb76ff1Sjsg if (ret)
61*1bb76ff1Sjsg return ret;
62*1bb76ff1Sjsg src_addr += current_copy_size;
63*1bb76ff1Sjsg dst_addr += current_copy_size;
64*1bb76ff1Sjsg mem_size -= current_copy_size;
65*1bb76ff1Sjsg }
66*1bb76ff1Sjsg
67*1bb76ff1Sjsg return 0;
68*1bb76ff1Sjsg }
69*1bb76ff1Sjsg
amdgpu_lsdma_fill_mem(struct amdgpu_device * adev,uint64_t dst_addr,uint32_t data,uint64_t mem_size)70*1bb76ff1Sjsg int amdgpu_lsdma_fill_mem(struct amdgpu_device *adev,
71*1bb76ff1Sjsg uint64_t dst_addr,
72*1bb76ff1Sjsg uint32_t data,
73*1bb76ff1Sjsg uint64_t mem_size)
74*1bb76ff1Sjsg {
75*1bb76ff1Sjsg int ret;
76*1bb76ff1Sjsg
77*1bb76ff1Sjsg if (mem_size == 0)
78*1bb76ff1Sjsg return -EINVAL;
79*1bb76ff1Sjsg
80*1bb76ff1Sjsg while (mem_size > 0) {
81*1bb76ff1Sjsg uint64_t current_fill_size = min(mem_size, AMDGPU_LSDMA_MAX_SIZE);
82*1bb76ff1Sjsg
83*1bb76ff1Sjsg ret = adev->lsdma.funcs->fill_mem(adev, dst_addr, data, current_fill_size);
84*1bb76ff1Sjsg if (ret)
85*1bb76ff1Sjsg return ret;
86*1bb76ff1Sjsg dst_addr += current_fill_size;
87*1bb76ff1Sjsg mem_size -= current_fill_size;
88*1bb76ff1Sjsg }
89*1bb76ff1Sjsg
90*1bb76ff1Sjsg return 0;
91*1bb76ff1Sjsg }
92