1*1bb76ff1Sjsg /* 2*1bb76ff1Sjsg * Copyright 2021 Advanced Micro Devices, Inc. 3*1bb76ff1Sjsg * 4*1bb76ff1Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*1bb76ff1Sjsg * copy of this software and associated documentation files (the "Software"), 6*1bb76ff1Sjsg * to deal in the Software without restriction, including without limitation 7*1bb76ff1Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*1bb76ff1Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*1bb76ff1Sjsg * Software is furnished to do so, subject to the following conditions: 10*1bb76ff1Sjsg * 11*1bb76ff1Sjsg * The above copyright notice and this permission notice shall be included in 12*1bb76ff1Sjsg * all copies or substantial portions of the Software. 13*1bb76ff1Sjsg * 14*1bb76ff1Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*1bb76ff1Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*1bb76ff1Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*1bb76ff1Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*1bb76ff1Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*1bb76ff1Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*1bb76ff1Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21*1bb76ff1Sjsg * 22*1bb76ff1Sjsg */ 23*1bb76ff1Sjsg 24*1bb76ff1Sjsg #ifndef __AMDGPU_IMU_H__ 25*1bb76ff1Sjsg #define __AMDGPU_IMU_H__ 26*1bb76ff1Sjsg 27*1bb76ff1Sjsg enum imu_work_mode { 28*1bb76ff1Sjsg DEBUG_MODE, 29*1bb76ff1Sjsg MISSION_MODE 30*1bb76ff1Sjsg }; 31*1bb76ff1Sjsg 32*1bb76ff1Sjsg struct amdgpu_imu_funcs { 33*1bb76ff1Sjsg int (*init_microcode)(struct amdgpu_device *adev); 34*1bb76ff1Sjsg int (*load_microcode)(struct amdgpu_device *adev); 35*1bb76ff1Sjsg void (*setup_imu)(struct amdgpu_device *adev); 36*1bb76ff1Sjsg int (*start_imu)(struct amdgpu_device *adev); 37*1bb76ff1Sjsg void (*program_rlc_ram)(struct amdgpu_device *adev); 38*1bb76ff1Sjsg int (*wait_for_reset_status)(struct amdgpu_device *adev); 39*1bb76ff1Sjsg }; 40*1bb76ff1Sjsg 41*1bb76ff1Sjsg struct imu_rlc_ram_golden { 42*1bb76ff1Sjsg u32 hwip; 43*1bb76ff1Sjsg u32 instance; 44*1bb76ff1Sjsg u32 segment; 45*1bb76ff1Sjsg u32 reg; 46*1bb76ff1Sjsg u32 data; 47*1bb76ff1Sjsg u32 addr_mask; 48*1bb76ff1Sjsg }; 49*1bb76ff1Sjsg 50*1bb76ff1Sjsg #define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \ 51*1bb76ff1Sjsg { ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask } 52*1bb76ff1Sjsg 53*1bb76ff1Sjsg struct amdgpu_imu { 54*1bb76ff1Sjsg const struct amdgpu_imu_funcs *funcs; 55*1bb76ff1Sjsg enum imu_work_mode mode; 56*1bb76ff1Sjsg }; 57*1bb76ff1Sjsg 58*1bb76ff1Sjsg #endif 59