xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1fb4d8502Sjsg /*
2fb4d8502Sjsg  * Copyright 2014 Advanced Micro Devices, Inc.
3fb4d8502Sjsg  *
4fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg  * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg  * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg  * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg  *
11fb4d8502Sjsg  * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg  * all copies or substantial portions of the Software.
13fb4d8502Sjsg  *
14fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17fb4d8502Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg  *
22fb4d8502Sjsg  */
23fb4d8502Sjsg 
24c349dbc7Sjsg #include <linux/dma-mapping.h>
25c349dbc7Sjsg 
26c349dbc7Sjsg #include <drm/drm_legacy.h>
27c349dbc7Sjsg 
28fb4d8502Sjsg #include "amdgpu.h"
29fb4d8502Sjsg #include "amdgpu_ih.h"
30fb4d8502Sjsg 
31fb4d8502Sjsg /**
32fb4d8502Sjsg  * amdgpu_ih_ring_init - initialize the IH state
33fb4d8502Sjsg  *
34fb4d8502Sjsg  * @adev: amdgpu_device pointer
35c349dbc7Sjsg  * @ih: ih ring to initialize
36c349dbc7Sjsg  * @ring_size: ring size to allocate
37c349dbc7Sjsg  * @use_bus_addr: true when we can use dma_alloc_coherent
38fb4d8502Sjsg  *
39fb4d8502Sjsg  * Initializes the IH state and allocates a buffer
40fb4d8502Sjsg  * for the IH ring buffer.
41fb4d8502Sjsg  * Returns 0 for success, errors for failure.
42fb4d8502Sjsg  */
amdgpu_ih_ring_init(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,unsigned ring_size,bool use_bus_addr)43c349dbc7Sjsg int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
44c349dbc7Sjsg 			unsigned ring_size, bool use_bus_addr)
45fb4d8502Sjsg {
46fb4d8502Sjsg 	u32 rb_bufsz;
47fb4d8502Sjsg 	int r;
48fb4d8502Sjsg 	struct drm_dmamem *dmah;
49fb4d8502Sjsg 	int flags = 0;
50fb4d8502Sjsg 
51fb4d8502Sjsg 	/* Align ring size */
52fb4d8502Sjsg 	rb_bufsz = order_base_2(ring_size / 4);
53fb4d8502Sjsg 	ring_size = (1 << rb_bufsz) * 4;
54c349dbc7Sjsg 	ih->ring_size = ring_size;
55c349dbc7Sjsg 	ih->ptr_mask = ih->ring_size - 1;
56c349dbc7Sjsg 	ih->rptr = 0;
57c349dbc7Sjsg 	ih->use_bus_addr = use_bus_addr;
58fb4d8502Sjsg 
59c349dbc7Sjsg 	if (use_bus_addr) {
60c349dbc7Sjsg 		dma_addr_t dma_addr;
61c349dbc7Sjsg 
62c349dbc7Sjsg 		if (ih->ring)
63c349dbc7Sjsg 			return 0;
64c349dbc7Sjsg 
65fb4d8502Sjsg 		/* add 8 bytes for the rptr/wptr shadows and
66fb4d8502Sjsg 		 * add them to the end of the ring allocation.
67fb4d8502Sjsg 		 */
68fb4d8502Sjsg #ifdef __linux__
69c349dbc7Sjsg 		ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
70c349dbc7Sjsg 					      &dma_addr, GFP_KERNEL);
71c349dbc7Sjsg 		if (ih->ring == NULL)
72fb4d8502Sjsg 			return -ENOMEM;
73fb4d8502Sjsg #else
74fb4d8502Sjsg 		dmah = drm_dmamem_alloc(adev->dmat,
75c349dbc7Sjsg 		    ih->ring_size + 8,
76fb4d8502Sjsg 		    PAGE_SIZE, 1,
77c349dbc7Sjsg 		    ih->ring_size + 8, flags, 0);
78fb4d8502Sjsg 		if (dmah == NULL)
79fb4d8502Sjsg 			return -ENOMEM;
80c349dbc7Sjsg 		ih->dmah = dmah;
81c349dbc7Sjsg 		dma_addr = dmah->map->dm_segs[0].ds_addr;
82c349dbc7Sjsg 		ih->ring = (volatile uint32_t *)dmah->kva;
83fb4d8502Sjsg #endif
84c349dbc7Sjsg 
85c349dbc7Sjsg 		ih->gpu_addr = dma_addr;
86c349dbc7Sjsg 		ih->wptr_addr = dma_addr + ih->ring_size;
87c349dbc7Sjsg 		ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
88c349dbc7Sjsg 		ih->rptr_addr = dma_addr + ih->ring_size + 4;
89c349dbc7Sjsg 		ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
90c349dbc7Sjsg 	} else {
91c349dbc7Sjsg 		unsigned wptr_offs, rptr_offs;
92c349dbc7Sjsg 
93c349dbc7Sjsg 		r = amdgpu_device_wb_get(adev, &wptr_offs);
94c349dbc7Sjsg 		if (r)
95c349dbc7Sjsg 			return r;
96c349dbc7Sjsg 
97c349dbc7Sjsg 		r = amdgpu_device_wb_get(adev, &rptr_offs);
98c349dbc7Sjsg 		if (r) {
99c349dbc7Sjsg 			amdgpu_device_wb_free(adev, wptr_offs);
100c349dbc7Sjsg 			return r;
101c349dbc7Sjsg 		}
102c349dbc7Sjsg 
103c349dbc7Sjsg 		r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
104c349dbc7Sjsg 					    AMDGPU_GEM_DOMAIN_GTT,
105c349dbc7Sjsg 					    &ih->ring_obj, &ih->gpu_addr,
106c349dbc7Sjsg 					    (void **)&ih->ring);
107c349dbc7Sjsg 		if (r) {
108c349dbc7Sjsg 			amdgpu_device_wb_free(adev, rptr_offs);
109c349dbc7Sjsg 			amdgpu_device_wb_free(adev, wptr_offs);
110c349dbc7Sjsg 			return r;
111c349dbc7Sjsg 		}
112c349dbc7Sjsg 
113c349dbc7Sjsg 		ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
114c349dbc7Sjsg 		ih->wptr_cpu = &adev->wb.wb[wptr_offs];
115c349dbc7Sjsg 		ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
116c349dbc7Sjsg 		ih->rptr_cpu = &adev->wb.wb[rptr_offs];
117fb4d8502Sjsg 	}
1185ca02815Sjsg 
1195ca02815Sjsg 	init_waitqueue_head(&ih->wait_process);
120fb4d8502Sjsg 	return 0;
121fb4d8502Sjsg }
122fb4d8502Sjsg 
123fb4d8502Sjsg /**
124fb4d8502Sjsg  * amdgpu_ih_ring_fini - tear down the IH state
125fb4d8502Sjsg  *
126fb4d8502Sjsg  * @adev: amdgpu_device pointer
127c349dbc7Sjsg  * @ih: ih ring to tear down
128fb4d8502Sjsg  *
129fb4d8502Sjsg  * Tears down the IH state and frees buffer
130fb4d8502Sjsg  * used for the IH ring buffer.
131fb4d8502Sjsg  */
amdgpu_ih_ring_fini(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)132c349dbc7Sjsg void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
133fb4d8502Sjsg {
1345ca02815Sjsg 
135c349dbc7Sjsg 	if (!ih->ring)
136c349dbc7Sjsg 		return;
137c349dbc7Sjsg 
1385ca02815Sjsg 	if (ih->use_bus_addr) {
1395ca02815Sjsg 
140fb4d8502Sjsg 		/* add 8 bytes for the rptr/wptr shadows and
141fb4d8502Sjsg 		 * add them to the end of the ring allocation.
142fb4d8502Sjsg 		 */
143fb4d8502Sjsg #ifdef __linux__
144c349dbc7Sjsg 		dma_free_coherent(adev->dev, ih->ring_size + 8,
145c349dbc7Sjsg 				  (void *)ih->ring, ih->gpu_addr);
146fb4d8502Sjsg #else
147c349dbc7Sjsg 		drm_dmamem_free(adev->dmat, ih->dmah);
148fb4d8502Sjsg #endif
149c349dbc7Sjsg 		ih->ring = NULL;
150fb4d8502Sjsg 	} else {
151c349dbc7Sjsg 		amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
152c349dbc7Sjsg 				      (void **)&ih->ring);
153c349dbc7Sjsg 		amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
154c349dbc7Sjsg 		amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
155fb4d8502Sjsg 	}
156fb4d8502Sjsg }
157fb4d8502Sjsg 
158fb4d8502Sjsg /**
1595ca02815Sjsg  * amdgpu_ih_ring_write - write IV to the ring buffer
1605ca02815Sjsg  *
161*f005ef32Sjsg  * @adev: amdgpu_device pointer
1625ca02815Sjsg  * @ih: ih ring to write to
1635ca02815Sjsg  * @iv: the iv to write
1645ca02815Sjsg  * @num_dw: size of the iv in dw
1655ca02815Sjsg  *
1665ca02815Sjsg  * Writes an IV to the ring buffer using the CPU and increment the wptr.
1675ca02815Sjsg  * Used for testing and delegating IVs to a software ring.
1685ca02815Sjsg  */
amdgpu_ih_ring_write(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,const uint32_t * iv,unsigned int num_dw)169*f005ef32Sjsg void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
170*f005ef32Sjsg 			  const uint32_t *iv, unsigned int num_dw)
1715ca02815Sjsg {
1725ca02815Sjsg 	uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;
1735ca02815Sjsg 	unsigned int i;
1745ca02815Sjsg 
1755ca02815Sjsg 	for (i = 0; i < num_dw; ++i)
1765ca02815Sjsg 	        ih->ring[wptr++] = cpu_to_le32(iv[i]);
1775ca02815Sjsg 
1785ca02815Sjsg 	wptr <<= 2;
1795ca02815Sjsg 	wptr &= ih->ptr_mask;
1805ca02815Sjsg 
1815ca02815Sjsg 	/* Only commit the new wptr if we don't overflow */
1825ca02815Sjsg 	if (wptr != READ_ONCE(ih->rptr)) {
1835ca02815Sjsg 		wmb();
1845ca02815Sjsg 		WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
185*f005ef32Sjsg 	} else if (adev->irq.retry_cam_enabled) {
186*f005ef32Sjsg 		dev_warn_once(adev->dev, "IH soft ring buffer overflow 0x%X, 0x%X\n",
187*f005ef32Sjsg 			      wptr, ih->rptr);
1885ca02815Sjsg 	}
1895ca02815Sjsg }
1905ca02815Sjsg 
1915ca02815Sjsg /**
1921bb76ff1Sjsg  * amdgpu_ih_wait_on_checkpoint_process_ts - wait to process IVs up to checkpoint
1935ca02815Sjsg  *
1945ca02815Sjsg  * @adev: amdgpu_device pointer
1955ca02815Sjsg  * @ih: ih ring to process
1965ca02815Sjsg  *
1975ca02815Sjsg  * Used to ensure ring has processed IVs up to the checkpoint write pointer.
1985ca02815Sjsg  */
amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)1991bb76ff1Sjsg int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
2005ca02815Sjsg 					struct amdgpu_ih_ring *ih)
2015ca02815Sjsg {
2021bb76ff1Sjsg 	uint32_t checkpoint_wptr;
2031bb76ff1Sjsg 	uint64_t checkpoint_ts;
2041bb76ff1Sjsg 	long timeout = HZ;
2055ca02815Sjsg 
2065ca02815Sjsg 	if (!ih->enabled || adev->shutdown)
2075ca02815Sjsg 		return -ENODEV;
2085ca02815Sjsg 
2095ca02815Sjsg 	checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
2101bb76ff1Sjsg 	/* Order wptr with ring data. */
2115ca02815Sjsg 	rmb();
2121bb76ff1Sjsg 	checkpoint_ts = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1);
2135ca02815Sjsg 
2141bb76ff1Sjsg 	return wait_event_interruptible_timeout(ih->wait_process,
2151bb76ff1Sjsg 		    amdgpu_ih_ts_after(checkpoint_ts, ih->processed_timestamp) ||
2161bb76ff1Sjsg 		    ih->rptr == amdgpu_ih_get_wptr(adev, ih), timeout);
2175ca02815Sjsg }
2185ca02815Sjsg 
2195ca02815Sjsg /**
220fb4d8502Sjsg  * amdgpu_ih_process - interrupt handler
221fb4d8502Sjsg  *
222fb4d8502Sjsg  * @adev: amdgpu_device pointer
223c349dbc7Sjsg  * @ih: ih ring to process
224fb4d8502Sjsg  *
225fb4d8502Sjsg  * Interrupt hander (VI), walk the IH ring.
226fb4d8502Sjsg  * Returns irq process return code.
227fb4d8502Sjsg  */
amdgpu_ih_process(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)228c349dbc7Sjsg int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
229fb4d8502Sjsg {
2305ca02815Sjsg 	unsigned int count;
231fb4d8502Sjsg 	u32 wptr;
232fb4d8502Sjsg 
233c349dbc7Sjsg 	if (!ih->enabled || adev->shutdown)
234fb4d8502Sjsg 		return IRQ_NONE;
235fb4d8502Sjsg 
236c349dbc7Sjsg 	wptr = amdgpu_ih_get_wptr(adev, ih);
237fb4d8502Sjsg 
238fb4d8502Sjsg restart_ih:
2395ca02815Sjsg 	count  = AMDGPU_IH_MAX_NUM_IVS;
240c349dbc7Sjsg 	DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
241fb4d8502Sjsg 
242fb4d8502Sjsg 	/* Order reading of wptr vs. reading of IH ring data */
243fb4d8502Sjsg 	rmb();
244fb4d8502Sjsg 
245c349dbc7Sjsg 	while (ih->rptr != wptr && --count) {
246c349dbc7Sjsg 		amdgpu_irq_dispatch(adev, ih);
247c349dbc7Sjsg 		ih->rptr &= ih->ptr_mask;
248fb4d8502Sjsg 	}
249fb4d8502Sjsg 
250c349dbc7Sjsg 	amdgpu_ih_set_rptr(adev, ih);
2515ca02815Sjsg 	wake_up_all(&ih->wait_process);
252fb4d8502Sjsg 
253fb4d8502Sjsg 	/* make sure wptr hasn't changed while processing */
254c349dbc7Sjsg 	wptr = amdgpu_ih_get_wptr(adev, ih);
255c349dbc7Sjsg 	if (wptr != ih->rptr)
256fb4d8502Sjsg 		goto restart_ih;
257fb4d8502Sjsg 
258fb4d8502Sjsg 	return IRQ_HANDLED;
259fb4d8502Sjsg }
260fb4d8502Sjsg 
2615ca02815Sjsg /**
2625ca02815Sjsg  * amdgpu_ih_decode_iv_helper - decode an interrupt vector
2635ca02815Sjsg  *
2645ca02815Sjsg  * @adev: amdgpu_device pointer
2655ca02815Sjsg  * @ih: ih ring to process
2665ca02815Sjsg  * @entry: IV entry
2675ca02815Sjsg  *
2685ca02815Sjsg  * Decodes the interrupt vector at the current rptr
2691bb76ff1Sjsg  * position and also advance the position for Vega10
2705ca02815Sjsg  * and later GPUs.
2715ca02815Sjsg  */
amdgpu_ih_decode_iv_helper(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,struct amdgpu_iv_entry * entry)2725ca02815Sjsg void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
2735ca02815Sjsg 				struct amdgpu_ih_ring *ih,
2745ca02815Sjsg 				struct amdgpu_iv_entry *entry)
2755ca02815Sjsg {
2765ca02815Sjsg 	/* wptr/rptr are in bytes! */
2775ca02815Sjsg 	u32 ring_index = ih->rptr >> 2;
2785ca02815Sjsg 	uint32_t dw[8];
2795ca02815Sjsg 
2805ca02815Sjsg 	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
2815ca02815Sjsg 	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
2825ca02815Sjsg 	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
2835ca02815Sjsg 	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
2845ca02815Sjsg 	dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
2855ca02815Sjsg 	dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
2865ca02815Sjsg 	dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
2875ca02815Sjsg 	dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
2885ca02815Sjsg 
2895ca02815Sjsg 	entry->client_id = dw[0] & 0xff;
2905ca02815Sjsg 	entry->src_id = (dw[0] >> 8) & 0xff;
2915ca02815Sjsg 	entry->ring_id = (dw[0] >> 16) & 0xff;
2925ca02815Sjsg 	entry->vmid = (dw[0] >> 24) & 0xf;
2935ca02815Sjsg 	entry->vmid_src = (dw[0] >> 31);
2945ca02815Sjsg 	entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
2955ca02815Sjsg 	entry->timestamp_src = dw[2] >> 31;
2965ca02815Sjsg 	entry->pasid = dw[3] & 0xffff;
297*f005ef32Sjsg 	entry->node_id = (dw[3] >> 16) & 0xff;
2985ca02815Sjsg 	entry->src_data[0] = dw[4];
2995ca02815Sjsg 	entry->src_data[1] = dw[5];
3005ca02815Sjsg 	entry->src_data[2] = dw[6];
3015ca02815Sjsg 	entry->src_data[3] = dw[7];
3025ca02815Sjsg 
3035ca02815Sjsg 	/* wptr/rptr are in bytes! */
3045ca02815Sjsg 	ih->rptr += 32;
3055ca02815Sjsg }
3061bb76ff1Sjsg 
amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring * ih,u32 rptr,signed int offset)3071bb76ff1Sjsg uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
3081bb76ff1Sjsg 				       signed int offset)
3091bb76ff1Sjsg {
3101bb76ff1Sjsg 	uint32_t iv_size = 32;
3111bb76ff1Sjsg 	uint32_t ring_index;
3121bb76ff1Sjsg 	uint32_t dw1, dw2;
3131bb76ff1Sjsg 
3141bb76ff1Sjsg 	rptr += iv_size * offset;
3151bb76ff1Sjsg 	ring_index = (rptr & ih->ptr_mask) >> 2;
3161bb76ff1Sjsg 
3171bb76ff1Sjsg 	dw1 = le32_to_cpu(ih->ring[ring_index + 1]);
3181bb76ff1Sjsg 	dw2 = le32_to_cpu(ih->ring[ring_index + 2]);
3191bb76ff1Sjsg 	return dw1 | ((u64)(dw2 & 0xffff) << 32);
3201bb76ff1Sjsg }
321