1*f005ef32Sjsg /*
2*f005ef32Sjsg * Copyright 2017 Advanced Micro Devices, Inc.
3*f005ef32Sjsg *
4*f005ef32Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5*f005ef32Sjsg * copy of this software and associated documentation files (the "Software"),
6*f005ef32Sjsg * to deal in the Software without restriction, including without limitation
7*f005ef32Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*f005ef32Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9*f005ef32Sjsg * Software is furnished to do so, subject to the following conditions:
10*f005ef32Sjsg *
11*f005ef32Sjsg * The above copyright notice and this permission notice shall be included in
12*f005ef32Sjsg * all copies or substantial portions of the Software.
13*f005ef32Sjsg *
14*f005ef32Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*f005ef32Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*f005ef32Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*f005ef32Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*f005ef32Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*f005ef32Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*f005ef32Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21*f005ef32Sjsg *
22*f005ef32Sjsg * Authors: Christian König
23*f005ef32Sjsg */
24*f005ef32Sjsg #ifndef __AMDGPU_MN_H__
25*f005ef32Sjsg #define __AMDGPU_MN_H__
26*f005ef32Sjsg
27*f005ef32Sjsg #include <linux/types.h>
28*f005ef32Sjsg #include <linux/hmm.h>
29*f005ef32Sjsg #include <linux/rwsem.h>
30*f005ef32Sjsg #include <linux/workqueue.h>
31*f005ef32Sjsg #include <linux/interval_tree.h>
32*f005ef32Sjsg #include <linux/mmu_notifier.h>
33*f005ef32Sjsg
34*f005ef32Sjsg int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier,
35*f005ef32Sjsg uint64_t start, uint64_t npages, bool readonly,
36*f005ef32Sjsg void *owner, struct vm_page **pages,
37*f005ef32Sjsg struct hmm_range **phmm_range);
38*f005ef32Sjsg bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range);
39*f005ef32Sjsg
40*f005ef32Sjsg #if defined(CONFIG_HMM_MIRROR)
41*f005ef32Sjsg int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr);
42*f005ef32Sjsg void amdgpu_hmm_unregister(struct amdgpu_bo *bo);
43*f005ef32Sjsg #else
amdgpu_hmm_register(struct amdgpu_bo * bo,unsigned long addr)44*f005ef32Sjsg static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr)
45*f005ef32Sjsg {
46*f005ef32Sjsg DRM_WARN_ONCE("HMM_MIRROR kernel config option is not enabled, "
47*f005ef32Sjsg "add CONFIG_ZONE_DEVICE=y in config file to fix this\n");
48*f005ef32Sjsg return -ENODEV;
49*f005ef32Sjsg }
amdgpu_hmm_unregister(struct amdgpu_bo * bo)50*f005ef32Sjsg static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {}
51*f005ef32Sjsg #endif
52*f005ef32Sjsg
53*f005ef32Sjsg #endif
54