1c349dbc7Sjsg /* 2c349dbc7Sjsg * Copyright 2018 Advanced Micro Devices, Inc. 3c349dbc7Sjsg * 4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"), 6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation 7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions: 10c349dbc7Sjsg * 11c349dbc7Sjsg * The above copyright notice and this permission notice shall be included in 12c349dbc7Sjsg * all copies or substantial portions of the Software. 13c349dbc7Sjsg * 14c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c349dbc7Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c349dbc7Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c349dbc7Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21c349dbc7Sjsg * 22c349dbc7Sjsg */ 23c349dbc7Sjsg #ifndef __AMDGPU_GEM_H__ 24c349dbc7Sjsg #define __AMDGPU_GEM_H__ 25c349dbc7Sjsg 26c349dbc7Sjsg #include <drm/amdgpu_drm.h> 27c349dbc7Sjsg #include <drm/drm_gem.h> 28c349dbc7Sjsg 29c349dbc7Sjsg /* 30c349dbc7Sjsg * GEM. 31c349dbc7Sjsg */ 32c349dbc7Sjsg 33c349dbc7Sjsg #define AMDGPU_GEM_DOMAIN_MAX 0x3 34c349dbc7Sjsg #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base) 35c349dbc7Sjsg 36c349dbc7Sjsg unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 37c349dbc7Sjsg 38c349dbc7Sjsg /* 39c349dbc7Sjsg * GEM objects. 40c349dbc7Sjsg */ 41c349dbc7Sjsg void amdgpu_gem_force_release(struct amdgpu_device *adev); 42c349dbc7Sjsg int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 43c349dbc7Sjsg int alignment, u32 initial_domain, 44c349dbc7Sjsg u64 flags, enum ttm_bo_type type, 45c349dbc7Sjsg struct dma_resv *resv, 46*f005ef32Sjsg struct drm_gem_object **obj, int8_t xcp_id_plus1); 47c349dbc7Sjsg int amdgpu_mode_dumb_create(struct drm_file *file_priv, 48c349dbc7Sjsg struct drm_device *dev, 49c349dbc7Sjsg struct drm_mode_create_dumb *args); 50c349dbc7Sjsg int amdgpu_mode_dumb_mmap(struct drm_file *filp, 51c349dbc7Sjsg struct drm_device *dev, 52c349dbc7Sjsg uint32_t handle, uint64_t *offset_p); 53c349dbc7Sjsg 54c349dbc7Sjsg int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 55c349dbc7Sjsg struct drm_file *filp); 56c349dbc7Sjsg int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 57c349dbc7Sjsg struct drm_file *filp); 58c349dbc7Sjsg int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 59c349dbc7Sjsg struct drm_file *filp); 60c349dbc7Sjsg int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 61c349dbc7Sjsg struct drm_file *filp); 62c349dbc7Sjsg int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 63c349dbc7Sjsg struct drm_file *filp); 64c349dbc7Sjsg uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags); 65c349dbc7Sjsg int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 66c349dbc7Sjsg struct drm_file *filp); 67c349dbc7Sjsg int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 68c349dbc7Sjsg struct drm_file *filp); 69c349dbc7Sjsg 70c349dbc7Sjsg int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 71c349dbc7Sjsg struct drm_file *filp); 72c349dbc7Sjsg 73c349dbc7Sjsg #endif 74