1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/pagemap.h> 30 #include <drm/drmP.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 #include "amdgpu_display.h" 34 35 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 36 { 37 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 38 39 if (robj) { 40 amdgpu_mn_unregister(robj); 41 amdgpu_bo_unref(&robj); 42 } 43 } 44 45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 46 int alignment, u32 initial_domain, 47 u64 flags, enum ttm_bo_type type, 48 struct reservation_object *resv, 49 struct drm_gem_object **obj) 50 { 51 struct amdgpu_bo *bo; 52 struct amdgpu_bo_param bp; 53 int r; 54 55 memset(&bp, 0, sizeof(bp)); 56 *obj = NULL; 57 /* At least align on page size */ 58 if (alignment < PAGE_SIZE) { 59 alignment = PAGE_SIZE; 60 } 61 62 bp.size = size; 63 bp.byte_align = alignment; 64 bp.type = type; 65 bp.resv = resv; 66 bp.preferred_domain = initial_domain; 67 retry: 68 bp.flags = flags; 69 bp.domain = initial_domain; 70 r = amdgpu_bo_create(adev, &bp, &bo); 71 if (r) { 72 if (r != -ERESTARTSYS) { 73 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 74 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 75 goto retry; 76 } 77 78 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 79 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 80 goto retry; 81 } 82 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 83 size, initial_domain, alignment, r); 84 } 85 return r; 86 } 87 *obj = &bo->gem_base; 88 89 return 0; 90 } 91 92 void amdgpu_gem_force_release(struct amdgpu_device *adev) 93 { 94 STUB(); 95 #if 0 96 struct drm_device *ddev = adev->ddev; 97 struct drm_file *file; 98 99 mutex_lock(&ddev->filelist_mutex); 100 101 list_for_each_entry(file, &ddev->filelist, lhead) { 102 struct drm_gem_object *gobj; 103 int handle; 104 105 WARN_ONCE(1, "Still active user space clients!\n"); 106 spin_lock(&file->table_lock); 107 idr_for_each_entry(&file->object_idr, gobj, handle) { 108 WARN_ONCE(1, "And also active allocations!\n"); 109 drm_gem_object_put_unlocked(gobj); 110 } 111 idr_destroy(&file->object_idr); 112 spin_unlock(&file->table_lock); 113 } 114 115 mutex_unlock(&ddev->filelist_mutex); 116 #endif 117 } 118 119 /* 120 * Call from drm_gem_handle_create which appear in both new and open ioctl 121 * case. 122 */ 123 int amdgpu_gem_object_open(struct drm_gem_object *obj, 124 struct drm_file *file_priv) 125 { 126 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 128 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 129 struct amdgpu_vm *vm = &fpriv->vm; 130 struct amdgpu_bo_va *bo_va; 131 #ifdef notyet 132 struct mm_struct *mm; 133 #endif 134 int r; 135 136 #ifdef notyet 137 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 138 if (mm && mm != current->mm) 139 return -EPERM; 140 #endif 141 142 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 143 abo->tbo.resv != vm->root.base.bo->tbo.resv) 144 return -EPERM; 145 146 r = amdgpu_bo_reserve(abo, false); 147 if (r) 148 return r; 149 150 bo_va = amdgpu_vm_bo_find(vm, abo); 151 if (!bo_va) { 152 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 153 } else { 154 ++bo_va->ref_count; 155 } 156 amdgpu_bo_unreserve(abo); 157 return 0; 158 } 159 160 void amdgpu_gem_object_close(struct drm_gem_object *obj, 161 struct drm_file *file_priv) 162 { 163 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 164 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 165 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 166 struct amdgpu_vm *vm = &fpriv->vm; 167 168 struct amdgpu_bo_list_entry vm_pd; 169 struct list_head list, duplicates; 170 struct ttm_validate_buffer tv; 171 struct ww_acquire_ctx ticket; 172 struct amdgpu_bo_va *bo_va; 173 int r; 174 175 INIT_LIST_HEAD(&list); 176 INIT_LIST_HEAD(&duplicates); 177 178 tv.bo = &bo->tbo; 179 tv.shared = true; 180 list_add(&tv.head, &list); 181 182 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 183 184 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 185 if (r) { 186 dev_err(adev->dev, "leaking bo va because " 187 "we fail to reserve bo (%d)\n", r); 188 return; 189 } 190 bo_va = amdgpu_vm_bo_find(vm, bo); 191 if (bo_va && --bo_va->ref_count == 0) { 192 amdgpu_vm_bo_rmv(adev, bo_va); 193 194 if (amdgpu_vm_ready(vm)) { 195 struct dma_fence *fence = NULL; 196 197 r = amdgpu_vm_clear_freed(adev, vm, &fence); 198 if (unlikely(r)) { 199 dev_err(adev->dev, "failed to clear page " 200 "tables on GEM object close (%d)\n", r); 201 } 202 203 if (fence) { 204 amdgpu_bo_fence(bo, fence, true); 205 dma_fence_put(fence); 206 } 207 } 208 } 209 ttm_eu_backoff_reservation(&ticket, &list); 210 } 211 212 /* 213 * GEM ioctls. 214 */ 215 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 216 struct drm_file *filp) 217 { 218 struct amdgpu_device *adev = dev->dev_private; 219 struct amdgpu_fpriv *fpriv = filp->driver_priv; 220 struct amdgpu_vm *vm = &fpriv->vm; 221 union drm_amdgpu_gem_create *args = data; 222 uint64_t flags = args->in.domain_flags; 223 uint64_t size = args->in.bo_size; 224 struct reservation_object *resv = NULL; 225 struct drm_gem_object *gobj; 226 uint32_t handle; 227 int r; 228 229 /* reject invalid gem flags */ 230 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 231 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 232 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 233 AMDGPU_GEM_CREATE_VRAM_CLEARED | 234 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 235 AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) 236 237 return -EINVAL; 238 239 /* reject invalid gem domains */ 240 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 241 return -EINVAL; 242 243 /* create a gem object to contain this object in */ 244 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 245 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 246 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 247 /* if gds bo is created from user space, it must be 248 * passed to bo list 249 */ 250 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 251 return -EINVAL; 252 } 253 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 254 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 255 size = size << AMDGPU_GDS_SHIFT; 256 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 257 size = size << AMDGPU_GWS_SHIFT; 258 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) 259 size = size << AMDGPU_OA_SHIFT; 260 else 261 return -EINVAL; 262 } 263 size = roundup(size, PAGE_SIZE); 264 265 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 266 r = amdgpu_bo_reserve(vm->root.base.bo, false); 267 if (r) 268 return r; 269 270 resv = vm->root.base.bo->tbo.resv; 271 } 272 273 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 274 (u32)(0xffffffff & args->in.domains), 275 flags, ttm_bo_type_device, resv, &gobj); 276 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 277 if (!r) { 278 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 279 280 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 281 } 282 amdgpu_bo_unreserve(vm->root.base.bo); 283 } 284 if (r) 285 return r; 286 287 r = drm_gem_handle_create(filp, gobj, &handle); 288 /* drop reference from allocate - handle holds it now */ 289 drm_gem_object_put_unlocked(gobj); 290 if (r) 291 return r; 292 293 memset(args, 0, sizeof(*args)); 294 args->out.handle = handle; 295 return 0; 296 } 297 298 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 299 struct drm_file *filp) 300 { 301 STUB(); 302 return -ENOSYS; 303 #if 0 304 struct ttm_operation_ctx ctx = { true, false }; 305 struct amdgpu_device *adev = dev->dev_private; 306 struct drm_amdgpu_gem_userptr *args = data; 307 struct drm_gem_object *gobj; 308 struct amdgpu_bo *bo; 309 uint32_t handle; 310 int r; 311 312 if (offset_in_page(args->addr | args->size)) 313 return -EINVAL; 314 315 /* reject unknown flag values */ 316 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 317 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 318 AMDGPU_GEM_USERPTR_REGISTER)) 319 return -EINVAL; 320 321 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 322 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 323 324 /* if we want to write to it we must install a MMU notifier */ 325 return -EACCES; 326 } 327 328 /* create a gem object to contain this object in */ 329 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 330 0, ttm_bo_type_device, NULL, &gobj); 331 if (r) 332 return r; 333 334 bo = gem_to_amdgpu_bo(gobj); 335 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 336 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 337 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 338 if (r) 339 goto release_object; 340 341 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 342 r = amdgpu_mn_register(bo, args->addr); 343 if (r) 344 goto release_object; 345 } 346 347 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 348 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 349 bo->tbo.ttm->pages); 350 if (r) 351 goto release_object; 352 353 r = amdgpu_bo_reserve(bo, true); 354 if (r) 355 goto free_pages; 356 357 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 358 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 359 amdgpu_bo_unreserve(bo); 360 if (r) 361 goto free_pages; 362 } 363 364 r = drm_gem_handle_create(filp, gobj, &handle); 365 /* drop reference from allocate - handle holds it now */ 366 drm_gem_object_put_unlocked(gobj); 367 if (r) 368 return r; 369 370 args->handle = handle; 371 return 0; 372 373 free_pages: 374 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); 375 376 release_object: 377 drm_gem_object_put_unlocked(gobj); 378 379 return r; 380 #endif 381 } 382 383 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 384 struct drm_device *dev, 385 uint32_t handle, uint64_t *offset_p) 386 { 387 struct drm_gem_object *gobj; 388 struct amdgpu_bo *robj; 389 390 gobj = drm_gem_object_lookup(filp, handle); 391 if (gobj == NULL) { 392 return -ENOENT; 393 } 394 robj = gem_to_amdgpu_bo(gobj); 395 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 396 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 397 drm_gem_object_put_unlocked(gobj); 398 return -EPERM; 399 } 400 *offset_p = amdgpu_bo_mmap_offset(robj); 401 drm_gem_object_put_unlocked(gobj); 402 return 0; 403 } 404 405 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 406 struct drm_file *filp) 407 { 408 union drm_amdgpu_gem_mmap *args = data; 409 uint32_t handle = args->in.handle; 410 memset(args, 0, sizeof(*args)); 411 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 412 } 413 414 /** 415 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 416 * 417 * @timeout_ns: timeout in ns 418 * 419 * Calculate the timeout in jiffies from an absolute timeout in ns. 420 */ 421 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 422 { 423 unsigned long timeout_jiffies; 424 ktime_t timeout; 425 426 /* clamp timeout if it's to large */ 427 if (((int64_t)timeout_ns) < 0) 428 return MAX_SCHEDULE_TIMEOUT; 429 430 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 431 if (ktime_to_ns(timeout) < 0) 432 return 0; 433 434 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 435 /* clamp timeout to avoid unsigned-> signed overflow */ 436 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 437 return MAX_SCHEDULE_TIMEOUT - 1; 438 439 return timeout_jiffies; 440 } 441 442 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 443 struct drm_file *filp) 444 { 445 union drm_amdgpu_gem_wait_idle *args = data; 446 struct drm_gem_object *gobj; 447 struct amdgpu_bo *robj; 448 uint32_t handle = args->in.handle; 449 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 450 int r = 0; 451 long ret; 452 453 gobj = drm_gem_object_lookup(filp, handle); 454 if (gobj == NULL) { 455 return -ENOENT; 456 } 457 robj = gem_to_amdgpu_bo(gobj); 458 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 459 timeout); 460 461 /* ret == 0 means not signaled, 462 * ret > 0 means signaled 463 * ret < 0 means interrupted before timeout 464 */ 465 if (ret >= 0) { 466 memset(args, 0, sizeof(*args)); 467 args->out.status = (ret == 0); 468 } else 469 r = ret; 470 471 drm_gem_object_put_unlocked(gobj); 472 return r; 473 } 474 475 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 476 struct drm_file *filp) 477 { 478 struct drm_amdgpu_gem_metadata *args = data; 479 struct drm_gem_object *gobj; 480 struct amdgpu_bo *robj; 481 int r = -1; 482 483 DRM_DEBUG("%d \n", args->handle); 484 gobj = drm_gem_object_lookup(filp, args->handle); 485 if (gobj == NULL) 486 return -ENOENT; 487 robj = gem_to_amdgpu_bo(gobj); 488 489 r = amdgpu_bo_reserve(robj, false); 490 if (unlikely(r != 0)) 491 goto out; 492 493 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 494 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 495 r = amdgpu_bo_get_metadata(robj, args->data.data, 496 sizeof(args->data.data), 497 &args->data.data_size_bytes, 498 &args->data.flags); 499 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 500 if (args->data.data_size_bytes > sizeof(args->data.data)) { 501 r = -EINVAL; 502 goto unreserve; 503 } 504 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 505 if (!r) 506 r = amdgpu_bo_set_metadata(robj, args->data.data, 507 args->data.data_size_bytes, 508 args->data.flags); 509 } 510 511 unreserve: 512 amdgpu_bo_unreserve(robj); 513 out: 514 drm_gem_object_put_unlocked(gobj); 515 return r; 516 } 517 518 /** 519 * amdgpu_gem_va_update_vm -update the bo_va in its VM 520 * 521 * @adev: amdgpu_device pointer 522 * @vm: vm to update 523 * @bo_va: bo_va to update 524 * @operation: map, unmap or clear 525 * 526 * Update the bo_va directly after setting its address. Errors are not 527 * vital here, so they are not reported back to userspace. 528 */ 529 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 530 struct amdgpu_vm *vm, 531 struct amdgpu_bo_va *bo_va, 532 uint32_t operation) 533 { 534 int r; 535 536 if (!amdgpu_vm_ready(vm)) 537 return; 538 539 r = amdgpu_vm_clear_freed(adev, vm, NULL); 540 if (r) 541 goto error; 542 543 if (operation == AMDGPU_VA_OP_MAP || 544 operation == AMDGPU_VA_OP_REPLACE) { 545 r = amdgpu_vm_bo_update(adev, bo_va, false); 546 if (r) 547 goto error; 548 } 549 550 r = amdgpu_vm_update_directories(adev, vm); 551 552 error: 553 if (r && r != -ERESTARTSYS) 554 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 555 } 556 557 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 558 struct drm_file *filp) 559 { 560 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 561 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 562 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 563 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 564 AMDGPU_VM_PAGE_PRT; 565 566 struct drm_amdgpu_gem_va *args = data; 567 struct drm_gem_object *gobj; 568 struct amdgpu_device *adev = dev->dev_private; 569 struct amdgpu_fpriv *fpriv = filp->driver_priv; 570 struct amdgpu_bo *abo; 571 struct amdgpu_bo_va *bo_va; 572 struct amdgpu_bo_list_entry vm_pd; 573 struct ttm_validate_buffer tv; 574 struct ww_acquire_ctx ticket; 575 struct list_head list, duplicates; 576 uint64_t va_flags; 577 int r = 0; 578 579 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 580 dev_dbg(&dev->pdev->dev, 581 "va_address 0x%LX is in reserved area 0x%LX\n", 582 args->va_address, AMDGPU_VA_RESERVED_SIZE); 583 return -EINVAL; 584 } 585 586 if (args->va_address >= AMDGPU_VA_HOLE_START && 587 args->va_address < AMDGPU_VA_HOLE_END) { 588 dev_dbg(&dev->pdev->dev, 589 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 590 args->va_address, AMDGPU_VA_HOLE_START, 591 AMDGPU_VA_HOLE_END); 592 return -EINVAL; 593 } 594 595 args->va_address &= AMDGPU_VA_HOLE_MASK; 596 597 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 598 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 599 args->flags); 600 return -EINVAL; 601 } 602 603 switch (args->operation) { 604 case AMDGPU_VA_OP_MAP: 605 case AMDGPU_VA_OP_UNMAP: 606 case AMDGPU_VA_OP_CLEAR: 607 case AMDGPU_VA_OP_REPLACE: 608 break; 609 default: 610 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 611 args->operation); 612 return -EINVAL; 613 } 614 615 INIT_LIST_HEAD(&list); 616 INIT_LIST_HEAD(&duplicates); 617 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 618 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 619 gobj = drm_gem_object_lookup(filp, args->handle); 620 if (gobj == NULL) 621 return -ENOENT; 622 abo = gem_to_amdgpu_bo(gobj); 623 tv.bo = &abo->tbo; 624 tv.shared = !!(abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID); 625 list_add(&tv.head, &list); 626 } else { 627 gobj = NULL; 628 abo = NULL; 629 } 630 631 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 632 633 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 634 if (r) 635 goto error_unref; 636 637 if (abo) { 638 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 639 if (!bo_va) { 640 r = -ENOENT; 641 goto error_backoff; 642 } 643 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 644 bo_va = fpriv->prt_va; 645 } else { 646 bo_va = NULL; 647 } 648 649 switch (args->operation) { 650 case AMDGPU_VA_OP_MAP: 651 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 652 args->map_size); 653 if (r) 654 goto error_backoff; 655 656 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 657 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 658 args->offset_in_bo, args->map_size, 659 va_flags); 660 break; 661 case AMDGPU_VA_OP_UNMAP: 662 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 663 break; 664 665 case AMDGPU_VA_OP_CLEAR: 666 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 667 args->va_address, 668 args->map_size); 669 break; 670 case AMDGPU_VA_OP_REPLACE: 671 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 672 args->map_size); 673 if (r) 674 goto error_backoff; 675 676 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 677 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 678 args->offset_in_bo, args->map_size, 679 va_flags); 680 break; 681 default: 682 break; 683 } 684 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 685 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 686 args->operation); 687 688 error_backoff: 689 ttm_eu_backoff_reservation(&ticket, &list); 690 691 error_unref: 692 drm_gem_object_put_unlocked(gobj); 693 return r; 694 } 695 696 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 697 struct drm_file *filp) 698 { 699 struct amdgpu_device *adev = dev->dev_private; 700 struct drm_amdgpu_gem_op *args = data; 701 struct drm_gem_object *gobj; 702 struct amdgpu_bo *robj; 703 int r; 704 705 gobj = drm_gem_object_lookup(filp, args->handle); 706 if (gobj == NULL) { 707 return -ENOENT; 708 } 709 robj = gem_to_amdgpu_bo(gobj); 710 711 r = amdgpu_bo_reserve(robj, false); 712 if (unlikely(r)) 713 goto out; 714 715 switch (args->op) { 716 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 717 struct drm_amdgpu_gem_create_in info; 718 void __user *out = u64_to_user_ptr(args->value); 719 720 info.bo_size = robj->gem_base.size; 721 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 722 info.domains = robj->preferred_domains; 723 info.domain_flags = robj->flags; 724 amdgpu_bo_unreserve(robj); 725 if (copy_to_user(out, &info, sizeof(info))) 726 r = -EFAULT; 727 break; 728 } 729 case AMDGPU_GEM_OP_SET_PLACEMENT: 730 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 731 r = -EINVAL; 732 amdgpu_bo_unreserve(robj); 733 break; 734 } 735 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 736 r = -EPERM; 737 amdgpu_bo_unreserve(robj); 738 break; 739 } 740 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 741 AMDGPU_GEM_DOMAIN_GTT | 742 AMDGPU_GEM_DOMAIN_CPU); 743 robj->allowed_domains = robj->preferred_domains; 744 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 745 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 746 747 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 748 amdgpu_vm_bo_invalidate(adev, robj, true); 749 750 amdgpu_bo_unreserve(robj); 751 break; 752 default: 753 amdgpu_bo_unreserve(robj); 754 r = -EINVAL; 755 } 756 757 out: 758 drm_gem_object_put_unlocked(gobj); 759 return r; 760 } 761 762 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 763 struct drm_device *dev, 764 struct drm_mode_create_dumb *args) 765 { 766 struct amdgpu_device *adev = dev->dev_private; 767 struct drm_gem_object *gobj; 768 uint32_t handle; 769 u32 domain; 770 int r; 771 772 args->pitch = amdgpu_align_pitch(adev, args->width, 773 DIV_ROUND_UP(args->bpp, 8), 0); 774 args->size = (u64)args->pitch * args->height; 775 args->size = roundup2(args->size, PAGE_SIZE); 776 domain = amdgpu_bo_get_preferred_pin_domain(adev, 777 amdgpu_display_supported_domains(adev)); 778 r = amdgpu_gem_object_create(adev, args->size, 0, domain, 779 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 780 ttm_bo_type_device, NULL, &gobj); 781 if (r) 782 return -ENOMEM; 783 784 r = drm_gem_handle_create(file_priv, gobj, &handle); 785 /* drop reference from allocate - handle holds it now */ 786 drm_gem_object_put_unlocked(gobj); 787 if (r) { 788 return r; 789 } 790 args->handle = handle; 791 return 0; 792 } 793 794 #if defined(CONFIG_DEBUG_FS) 795 796 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ 797 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 798 seq_printf((m), " " #flag); \ 799 } 800 801 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 802 { 803 struct drm_gem_object *gobj = ptr; 804 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 805 struct seq_file *m = data; 806 807 struct dma_buf_attachment *attachment; 808 struct dma_buf *dma_buf; 809 unsigned domain; 810 const char *placement; 811 unsigned pin_count; 812 813 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 814 switch (domain) { 815 case AMDGPU_GEM_DOMAIN_VRAM: 816 placement = "VRAM"; 817 break; 818 case AMDGPU_GEM_DOMAIN_GTT: 819 placement = " GTT"; 820 break; 821 case AMDGPU_GEM_DOMAIN_CPU: 822 default: 823 placement = " CPU"; 824 break; 825 } 826 seq_printf(m, "\t0x%08x: %12ld byte %s", 827 id, amdgpu_bo_size(bo), placement); 828 829 pin_count = READ_ONCE(bo->pin_count); 830 if (pin_count) 831 seq_printf(m, " pin count %d", pin_count); 832 833 dma_buf = READ_ONCE(bo->gem_base.dma_buf); 834 attachment = READ_ONCE(bo->gem_base.import_attach); 835 836 if (attachment) 837 seq_printf(m, " imported from %p", dma_buf); 838 else if (dma_buf) 839 seq_printf(m, " exported as %p", dma_buf); 840 841 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 842 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); 843 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); 844 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); 845 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); 846 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 847 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); 848 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); 849 850 seq_printf(m, "\n"); 851 852 return 0; 853 } 854 855 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 856 { 857 struct drm_info_node *node = (struct drm_info_node *)m->private; 858 struct drm_device *dev = node->minor->dev; 859 struct drm_file *file; 860 int r; 861 862 r = mutex_lock_interruptible(&dev->filelist_mutex); 863 if (r) 864 return r; 865 866 list_for_each_entry(file, &dev->filelist, lhead) { 867 struct task_struct *task; 868 869 /* 870 * Although we have a valid reference on file->pid, that does 871 * not guarantee that the task_struct who called get_pid() is 872 * still alive (e.g. get_pid(current) => fork() => exit()). 873 * Therefore, we need to protect this ->comm access using RCU. 874 */ 875 rcu_read_lock(); 876 task = pid_task(file->pid, PIDTYPE_PID); 877 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 878 task ? task->comm : "<unknown>"); 879 rcu_read_unlock(); 880 881 spin_lock(&file->table_lock); 882 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 883 spin_unlock(&file->table_lock); 884 } 885 886 mutex_unlock(&dev->filelist_mutex); 887 return 0; 888 } 889 890 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 891 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 892 }; 893 #endif 894 895 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 896 { 897 #if defined(CONFIG_DEBUG_FS) 898 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 899 #endif 900 return 0; 901 } 902